1. Introduction

Nowadays, several PC form factors exist in the PC board market, such as NLX, LPX, ATX and Baby-AT form factors. Due to the different placements of the form factor, PC chipsets should be prepared for different board layouts. As a result, SiS chips based on compatible logic design provide two series of chipsets, SiS 5597 and SiS 5598, to assist board designers for their board layouts.

SiS 5597’s pin assignment is based on NLX, and LPX form factor, while SiS 5598’s is defined on the basis of ATX and Baby-AT form factors. In the next few chapters, you will read "SiS Chip" which indicates either SiS 5597 or 5598 chipsets, decided by the placements of form factors on PC boards of customers.

The SiS Chip with built-in VGA controller is a highly integrated single chip solution for Pentium PCI/ISA system. A portion of on-board DRAM is shared with the integrated VGA controller. In that way, the system cost is substantially reduced and on-board DRAM can be used flexibly.

The SiS Chip consists of Host-to-PCI bridge function, PCI to ISA bridge function, PCI IDE function, Universal Serial Bus host/hub function, Integrated RTC, Integrated Keyboard Controller and Graphics/Video accelerate function.

SiS Chip supports Enhanced Power Management, including legacy Power Management Unit and Advanced Configuration and Power Interface (ACPI). It also supports ATA Synchronous DMA transfer protocol to improve the IDE performance and Common Architecture for moving ISA function to PCI to improve system performance. The system block diagram is shown below :



2. Features

• Support Intel Pentium CPU and other compatible CPU host bus at 50/55/60/66/75 MHz
• Support CPU with MMX feature
• Support the Pipelined Address Mode of Pentium CPU
• Support the Full 64-bit Pentium Processor data Bus
• Meet PC97 Requirements
• Integrated Second Level ( L2 ) Cache Controller

• Integrated DRAM Controller

• Integrated PMU Controller

• Provides High Performance PCI Arbiter.

• Integrated Host-to-PCI Bridge

• Integrated Posted Write Buffers and Read Prefetch Buffers to Increase System Performance

• Integrated Video/Graphics Accelerator

• Integrated PCI-to-ISA Bridge

• Enhanced DMA Functions

• Built-in Two 8259A Interrupt Controllers

• Three Programmable 16-bit Counters compatible with 8254

• Built-in Keyboard Controller

• Built-in Real Time Clock(RTC) with 256B CMOS SRAM

• Fast PCI IDE Master/Slave Controller

• Universal Serial Bus Host Controller

• Support I2C serial Bus
• Support the Reroutibility of the four PCI Interrupts
• Support 2Mb Flash ROM Interface
• Support Signature Analysis for automatic test for VGA controller
• Support NAND Tree for ball connectivity testing
• 553-Balls BGA Package
• 0.35m 3.3V Technology

• Built-in 64x64x2 bit-mapped hardware cursor
• Built-in 6 stages PCI post write-buffer and 128 bits read-ahead cache to minimize wait-states in video memory access

• Built-in 64x64 CRT FIFOs with multiple scan lines prefetch capability to improve integration VGA performance
• Support Memory-mapped I/O
• Support linear addressing mode up to 4MByte to speed up graphics performance

• Support virtual screen up to 2048x2048
• Support 80/132 columns text mode in 25, 30, 44 or 60 rows and other modes

KEN#/INV	OSCI/IRQ8#	GPIO7/OCO#/OCI2#
RAS[5:0]#/CS[5:0]#	OSCO/RTCCS#	GPIO8/OCI1#
CAS[7:0]#/DQM[7:0]	ONCTL#/RTCALE	GPIO9/THRM#/IOCHK#
MA12/GPO3	KBDAT/IRQ1	GPIO10/ACPILED
MA13/GPO4	KBCLK/GPIO2	EXTSMI#/TURBO
MA14/GPO6	KLOCK#/GPIO0/RAMWC#	GPCS1/SIRQ
MA1B/SCAS1#	PMCLK/GPIO1	IDA[15:0]/SD[15:0]
MA0B/SRAS1#	PMDAT/IRQ12	IDB[8:0]/SA[16:8]
	IIRQ[A:B]/IRQ[14:15]	IDB[15:9]/LA[23:17]

1. Functional Description

1. Host Interface

The SiS Chip is designed to support Pentium CPU host interface at 75/66.667/60/55/50MHz. The host data bus and the DRAM bus are 64-bit wide.

The SiS Chip supports the pipelined addressing mode of the Pentium CPU by issuing the next address signal, NA#. NA# signal is asserted except single read DRAM cycle.

The SiS Chip supports the CPU L1 write back (WB) or write through (WT) cache policies and the SiS Chip L2 WB cache policies. The L1 cache is snooped by the assertion of EADS# when the CPU is put in the HOLD state.

The SiS Chip issues AHOLD to the Pentium CPU in response to the assertion of PCI master requests. Once the AHOLD is asserted, SiS Chip does not immediately assert PGNT[3:0]# until both the CPU to PCI posted write buffer and the memory write buffer are empty. During inquire cycles, the AHOLD may be negated temporarily to allow the CPU to write back the inquired hit modified line to L2 or DRAM.

 

2. Cache Controller

The built-in L2 Cache Controller uses a direct-mapped scheme, which can be configured as in the write back mode. SiS chip also supports the write through mode, but this function only for the cache sizing. Pipelined burst SRAMs are supported.

SiS Chip supports SRAM types auto-detection and auto-sizing. Table 3-1 shows the cache sizes that are supported by the SiS Chip when using synchronous SRAM, with the corresponding TAG RAM sizes, data RAM sizes, and cacheable memory sizes.

 

Table -1 Cache Size with 8-bit tag

Cache Size	Data RAM	Tag RAM	Cacheable Size
256K	32Kx32x2	8Kx8	64MB
512K	32Kx32x4	16Kx8	128MB
512K	64Kx32x2	16Kx8	128MB

The SiS Chip also provides an alternative to save the dirty SRAM chip. This is accomplished by integrated 16Kb Dirty RAM.

4. DRAM Controller

1. DRAM Type

The SiS Chip can support up to 384MBytes of DRAMs size and each bank could be single or double sided 64 bits FPM (Fast Page mode) DRAM, EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM) DRAM. Half populated bank(32-bit) is also supported.

The installed EDO/FPM DRAM type can be 256K, 512k, 1M, 2M, 4M, 8M or 16M bit deep by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM are supported. It also supports SDRAM 1M, 2M, 4M, 8M, 16M or 32M bit deep by n bit wide DRAMs, and both single and double sided. It is also permissible to mix the DRAMs (FPM/EDO/SDRAM) bank by bank and the corresponding DRAM timing will be switched automatically according to register settings.

 

2. DRAM Configuration

SiS Chip supports six rows of DRAMs each 64 bits wide. Regarding to these six row lines, BANK0 use RAS[1:0], BANK1 use RAS[3:2], BANK2 use RAS[5:4]. The six rows of DRAMs may be implemented in three banks of single-sided SIMMs for FPM/EDO DRAM, three banks of double-sided SIMMs , three banks of SDRAM or any other combinations as required. Access to the rows are not interleaved and need not to be populated starting from row 0 or in consecutive sequence.

The SiS Chip can support EDO, FPM and SDRAM. SDRAM, EDO and FPM DRAMs can not be mixed in one bank, however, different banks can use different types of DRAM..

The basic configurations are shown as the following sections:

 

EDO/FPM DRAM Configuration (4 SIMM/6 SIMM):



 

 

SDRAM Configuration (2 DIMM/3 DIMM):



 

DRAM Type Mixed Configuration: EDO/FPM + SDRAM (4 SIMM + 2 DIMM)

NOTE : 1. SiS Chip only support six rows (3 banks) DRAMs.

2. It is recommended that board designer must follow DC characteristics of each type

DRAM (SDRAM, EDO, FPM) to design the portion of DRAM in DRAM mode

mixed configuration.

3. SiS Chip will assert the RAS0#/CS0#, MA0A, MA1A, SCAS0, and SRAS0 (Bank

0) when integrated VGA controller access the main memory.

4. If the KLOCK# or GPIO function are not needed, the Bank2 DRAM can used the RAMWC# instead of RAMWB#.

5. Please refer to "Multiplexed pins" section to define the pin for each function.

3. DRAM Scramble Table

The DRAM scramble table contains information for memory address mapping. These tables provide the translation between CPU host address and memory Row and Column address.

There are several memory address mapping: 64-bit mapping and 32-bit mapping for FPM/EDO DRAM, 2 Banks and 4 Banks mapping for SDRAM that SiS Chip supports:

 

64-bit mapping table for FPM/EDO DRAM

a. Symmetric:

Type	256K (9x9)		1M (10x10)		4M (11x11)		16M (12x12)
Address	Row	Column	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3	15	3
MA1	16	4	16	4	16	4	16	4
MA2	17	5	17	5	17	5	17	5
MA3	18	6	18	6	18	6	18	6
MA4	19	7	19	7	19	7	19	7
MA5	20	8	20	8	20	8	20	8
MA6	12	9	21	9	21	9	21	9
MA7	13	10	22	10	22	10	22	10
MA8	14	11	14	11	23	11	23	11
MA9	NA	NA	13	12	24	12	24	12
MA10	NA	NA	NA	NA	14	13	25	13
MA11	NA	NA	NA	NA	NA	NA	26	14

 

b. Asymmetric:

Type	512K (10x9)		1M (11x9)		2M (11x10)
Address	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3
MA1	16	4	16	4	16	4
MA2	17	5	17	5	17	5
MA3	18	6	18	6	18	6
MA4	19	7	19	7	19	7
MA5	20	8	20	8	20	8
MA6	21	9	21	9	21	9
MA7	13	10	22	10	22	10
MA8	14	11	14	11	23	11
MA9	12	NA	12	NA	13	12
MA10	NA	NA	13	NA	14	NA
MA11	NA	NA	NA	NA	NA	NA

 

Type	1M (12x8)		2M (12x9)		4M (12x10)		8M (12x11)
Address	Row	Column	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3	15	3
MA1	16	4	16	4	16	4	16	4
MA2	17	5	17	5	17	5	17	5
MA3	18	6	18	6	18	6	18	6
MA4	19	7	19	7	19	7	19	7
MA5	20	8	20	8	20	8	20	8
MA6	21	9	21	9	21	9	21	9
MA7	22	10	22	10	22	10	22	10
MA8	11	NA	23	11	23	11	23	11
MA9	12	NA	12	NA	24	12	24	12
MA10	13	NA	13	NA	13	NA	25	13
MA11	14	NA	14	NA	14	NA	14	NA

 

 

32-bit mapping table for FPM/EDO DRAM

a. Symmetric:

Type	256K (9x9)		1M (10x10)		4M (11x11)		16M (12x12)
Address	Row	Column	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3	15	3
MA1	16	4	16	4	16	4	16	4
MA2	17	5	17	5	17	5	17	5
MA3	18	6	18	6	18	6	18	6
MA4	19	7	19	7	19	7	19	7
MA5	11	8	20	8	20	8	20	8
MA6	12	9	21	9	21	9	21	9
MA7	13	2	13	2	22	2	22	2
MA8	14	10	14	10	23	10	23	10
MA9	NA	NA	12	11	13	11	24	11
MA10	NA	NA	NA	NA	14	12	25	12
MA11	NA	NA	NA	NA	NA	NA	14	13

 

b. Asymmetric:

Type	512K (10x9)		1M (11x9)		2M (11x10)
Address	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3
MA1	16	4	16	4	16	4
MA2	17	5	17	5	17	5
MA3	18	6	18	6	18	6
MA4	19	7	19	7	19	7
MA5	20	8	20	8	20	8
MA6	14	9	21	9	21	9
MA7	13	2	13	2	22	2
MA8	11	10	11	10	14	10
MA9	12	NA	12	NA	12	11
MA10	NA	NA	14	NA	13	NA
MA11	NA	NA	NA	NA	NA	NA

Type	1M (12x8)		2M (12x9)		4M (12x10)		8M (12x11)
Address	Row	Column	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3	15	3
MA1	16	4	16	4	16	4	16	4
MA2	17	5	17	5	17	5	17	5
MA3	18	6	18	6	18	6	18	6
MA4	19	7	19	7	19	7	19	7
MA5	20	8	20	8	20	8	20	8
MA6	21	9	21	9	21	9	21	9
MA7	10	2	22	2	22	2	22	2
MA8	11	NA	11	10	23	10	23	10
MA9	12	NA	12	NA	12	11	24	11
MA10	13	NA	13	NA	13	NA	13	12
MA11	14	NA	14	NA	14	NA	14	NA

 

MA Mapping table for SDRAM

a. 2 Banks Device SDRAM Type:

Type	1M (1x11x8)		2M (1x11x9)		4M (1x11x10)
Address	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3
MA1	16	4	16	4	16	4
MA2	17	5	17	5	17	5
MA3	18	6	18	6	18	6
MA4	19	7	19	7	19	7
MA5	20	8	20	8	20	8
MA6	21	9	21	9	21	9
MA7	22	10	22	10	22	10
MA8	12	NA	23	11	23	11
MA9	13	NA	13	NA	24	12
MA10	14	NA	14	NA	14	NA
MA11	11	11	12	12	13	13
MA12	NA	NA	NA	NA	NA	NA
MA13	NA	NA	NA	NA	NA	NA
MA14	NA	NA	NA	NA	NA	NA

Type	4M (1x13x8)		8M (1x13x9)		16M (1x13x10)
Address	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3
MA1	16	4	16	4	16	4
MA2	17	5	17	5	17	5
MA3	18	6	18	6	18	6
MA4	19	7	19	7	19	7
MA5	20	8	20	8	20	8
MA6	21	9	21	9	21	9
MA7	22	10	22	10	22	10
MA8	12	NA	23	11	23	11
MA9	13	NA	13	NA	24	12
MA10	14	NA	14	NA	14	NA
MA11	11	11	12	12	13	13
MA12	NA	NA	NA	NA	NA	NA
MA13	23	NA	24	NA	25	NA
MA14	24	NA	25	NA	26	NA

 

b. 4 banks Device SDRAM Type:

Type	2M (2x11x8))		4M (2x12x8)		8M (2x12x9)		16M (2x12x10)
Address	Row	Column	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3	15	3
MA1	16	4	16	4	16	4	16	4
MA2	17	5	17	5	17	5	17	5
MA3	18	6	18	6	18	6	18	6
MA4	19	7	19	7	19	7	19	7
MA5	20	8	20	8	20	8	20	8
MA6	21	9	21	9	21	9	21	9
MA7	22	10	22	10	22	10	22	10
MA8	23	NA	23	NA	23	11	23	11
MA9	13	NA	13	NA	24	NA	24	12
MA10	14	NA	14	NA	14	NA	25	NA
MA11	11	11	11	11	12	12	13	13
MA12	12	12	12	12	13	13	14	14
MA13	NA	NA	24	NA	25	NA	26	NA
MA14	NA	NA	NA	NA	NA	NA	NA	NA

Type	8M (2x13x8)		16M (2x13x9)		32M (2x13x10)
Address	Row	Column	Row	Column	Row	Column
MA0	15	3	15	3	15	3
MA1	16	4	16	4	16	4
MA2	17	5	17	5	17	5
MA3	18	6	18	6	18	6
MA4	19	7	19	7	19	7
MA5	20	8	20	8	20	8
MA6	21	9	21	9	21	9
MA7	22	10	22	10	22	10
MA8	23	NA	23	11	23	11
MA9	13	NA	24	NA	24	12
MA10	14	NA	14	NA	25	NA
MA11	11	11	12	12	13	13
MA12	12	12	13	13	14	14
MA13	24	NA	25	NA	26	NA
MA14	25	NA	26	NA	27	NA

 

4. DRAM Detection Sequence

SiS Chip supports six rows (three banks) DRAMs for DRAM’s SIMMs/DIMMs from row0 to row5. The DRAMs detection sequence is a row-based detection sequence, it is performed by the BIOS row by row and fulfill the DRAM configuration information into the corresponding DRAM configuration registers. The following steps will be described the DRAM detection sequence.

Step 1. To detect if there is any DRAM populated in row N, SiS Chip set this row with maximum DRAM size, then write/read the same address with test pattern by the normal DRAM read/write timing and compare the data. If the read data is the same as the write pattern, then there exists DRAM in the rowN; otherwise, proceed the SDRAM detection from step 3.

Step 2. If the DRAM is detected in the rowN by step 1, SiS Chip treat it as EDO or FPM DRAM. SiS Chip first write test pattern into DRAM, then set register 55h bit 6 (EDO test bit) to be "1" in PCI/memory bridge configuration register, and do the read, compare test pattern from the same DRAM location. The EDO test bit will delay the data forward to CPU after 4096 CPU clock. If the CPU still get the right data, then EDO mode DRAM is set to this row; otherwise, the FP mode DRAM is set. Go to step 8.

Step 3. If the DRAM is detected not populated in row N by normal write/read procedure, SiS Chip check if there is SDRAM exist in this row or not. SiS Chip first assume the DRAM mode is SDRAM (set bit [7:6] of register 60h/61h/62h to be "11" in Host to PCI bridge configuration register, it depends on which bank is under detection), and then do the SDRAM initialization procedure from step 4 to step 7.

Step 4. Set register 56h bit 3 to "1" to enable SDRAM sizing, then set register 57h bit 7 to be "1", register 57h bit 7 will drive a precharge command to SDRAM, then disable this bit (set to be "0").

Step 5. Set register 57h bit 6 to be "1", this bit will drive a "mode register set" (MRS) command to SDRAM. When SDRAM receive MRS command, it will load the needed information (Toggle/Linear mode, CAS Latency) into SDRAM. After doing MRS, disable this bit ( set to be "0").

Step 6. Set register 57h bit 5 to be "1" at least two times, then SDRAM will perform refresh cycle at least two times before the normal operation. Disable this bit ( set to be "0").

Step 7. Write/Read the test pattern into SDRAM, then compare the data. If the data is correct, SDRAM is detected, and set rowN as SDRAM; otherwise, rowN is no DRAM populated. Set Register 56h bit 3 to "0".

Step 8. After DRAM mode is set, SiS Chip do DRAM sizing by write/read test pattern based on the MA mapping table.

Step 9. Repeat from step 1 to step 8 to detect the other rows.

Note : The value of N is from 0 to 5.

The following will be shown the flow chart of DRAM Detection Sequence.



Figure -1

5. DRAM Performance

All the DRAM cycles are synchronous with the CPU clock. The following table shows the different possible speed settings that depend on different DRAM type, RAS# setting, CAS# setting, and so forth.

Cycle Type	DRAM type	75Mhz	66/60/50 Mhz	Note
Read Page Hit	EDO	5-2-2-2	5-2-2-2
	FPM	5-3-3-3	5-3-3-3	*1
	SDRAM	6-1-1-1	6-1-1-1	CL=2
		7-1-1-1	7-1-1-1	CL=3
Read Row Start	EDO	9-2-2-2	8-2-2-2	*2
	FPM	9-3-3-3	8-3-3-3	*1
	SDRAM	10-1-1-1	9-1-1-1	CL=2
		11-1-1-1	10-1-1-1	CL=3
Read Page Miss	EDO	13-2-2-2	12-2-2-2	*3, *4
	FPM	13-3-3-3	12-3-3-3	*1 *3 *4
	SDRAM	11-1-1-1	10-1-1-1	CL=2, *4
		12-1-1-1	11-1-1-1	CL=3, *4
Back-to-Back Burst Read Page Hit	EDO	5-2-2-2-2-2-2-2...	5-2-2-2-2-2-2-2...
	FPM	5-3-3-3-3-3-3-3...	5-3-3-3-3-3-3-3...
	SDRAM	6-1-1-1-2-1-1-1...	6-1-1-1-2-1-1-1...	CL=2, *5
		7-1-1-1-3-1-1-1...	7-1-1-1-3-1-1-1...	CL=3, *5
Posted Write	EDO/FPM/ SDRAM	3-1-1-1	3-1-1-1
Write Retire Rate	EDO	2-2-2	2-2-2
(Buffer to DRAM)	FPM	3-3-3	3-3-3	*1
	SDRAM	2-2-2	1-1-1/2-2-2	CL=2
			1-1-1/2-2-2	CL=3
Write Page Hit	EDO	2	2
	FPM	2	2
	SDRAM	2	2	CL=2
		2	2	CL=3
Write Row Start	EDO	7	6
	FPM	7	6
	SDRAM	7	6	CL=2
		7	6	CL=3
Write Page Miss	EDO	10	9
	FPM	10	9
	SDRAM	10	9	CL=2
		10	9	CL=3

Note: EDO CAS# width=1T, FPM CAS# width=2T, CAS precharge time=1T, 60ns DRAM.

*1 X-4-4-4 is for both CAS pulse width and CAS precharge time are 2 CPU clocks.

*2 It is for RAS to CAS time of 3 CPU clocks.

*3 It is for RAS pre-charge time of 4 CPU clocks, RAS to CAS time of 3 CPU clocks.

*4 EDO : 9-2-2-2, FPM : 9-3-3-3 and SDRAM : 8-1-1-1 during pipelined cycle.

*5 6-1-1-1-4-1-1-1 and 7-1-1-1-5-1-1-1 for L2 Cache is populated.

6. CPU to DRAM Posted Write FIFOs

There is a built-in CPU to Memory posted write buffer with 8 QWord deep ( CTMFF). All the write access to DRAM will be buffered. For the CPU read miss / Line fill cycles, the write-back data from the second level cache will be buffered first, and right after the data had been posted write into the FIFO, CPU can performs the read operation by the memory controller starting to read data from DRAMs. The buffered data are then written to DRAM whenever no any other read DRAM request comes. With this concurrent write back policy, many wait states are eliminated. If there comes a bunch of continuous DRAM write cycles, some ones will be pending if the CTMFF is full.

 

7. 32-bit (Half-Populated) DRAM Access

For the read access, there will be either single or burst read cycle to access the DRAM which depends on the cacheability of the cycle. If the current DRAM configuration is half-populated bank, then the SiS Chip will assert 8 consecutive cycles to access DRAM for the burst cycle. For the single cycle that only accesses DRAM within a DWord, the SiS Chip will only issue one cycle to access DRAM. For the single cycle that accesses one Qword or cross DWord boundary, the SiS Chip will issue two consecutive cycles to access DRAM.

 

8. Arbiter

The arbiter is the interface between the DRAM controller and the host which can access DRAMs. In addition to pass or translate the information from outside to DRAM controller, arbiter is also responsible for which master has higher priority to access DRAMs. The arbiter treats different DRAM access request as DRAM master, and that makes there be 5 masters which are trying to access DRAMs by sending their request to the arbiter. After one of them get the grant from the arbiter, it owns DRAM bus and begins to do memory data transaction.

The masters are: CPU read request, PCI master, Posted write FIFO write request, VGA request and Refresh request. The order of these masters shown above also stands for their priority to access memory.

 

9. Refresh cycle

The refresh cycle will occur every 15.6 us, 62.4 us, 124.8 us and 187.2 us and depend on setting the register 53h bits[2:1] in Host to PCI bridge configuration space. It is timed by a counter of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and the RAS[5:0]# are asserted sequentially.

6. PCI bridge

SiS Chip is able to operate at both asynchronous and synchronous PCI clocks. Synchronous mode is provided for those synchronous system to improve the overall system performance.

While in the PCI master write cycles, post-write is always performed. And function of Write Merge with CPU-to-DRAM post-write buffer is incorporated to eliminate the penalty of snooping write-back. On the other hand, prefetch is enabled for master read cycles by default, and such function could be disabled optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is implemented to eliminate the overhead of snooping write-back also.

In addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the overhead of inquiry cycles for master to main memory cycles. These key functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the purpose of zero wait for PCI burst transfer.

The post-write and prefetch buffers are both 16 Double-Word deep FIFOs .

 

1. Snooping Control

In order to maintain the cache consistency while PCI master accesses to main memory, SiS Chip performs inquiry cycle to snoop L1 and L2 caches before PCI masters really read from or write to memory. For the purpose of snooping, AHOLD is asserted to force the Pentium-like processors to float its address bus as soon as PCI master requests the PCI bus. Such host bus hold mechanism is completed by an AHOLD/BOFF# process and will be depicted later. Since the inquiry cycle is the major penalty for PCI master cycles, SiS Chip builds in a high performance snoop-ahead mechanism to incorporate the zero wait requirement of PCI bus transactions.

The main idea of "snoop-ahead" is to do memory operations and inquiry cycle simultaneously. For example, when transferring the Ln line of data, SiS Chip also performs the Ln+1 line of inquiry cycle in the mean while.

 

2. AHOLD/BOFF# Process and Arbiter Interface

In order to perform inquiry cycles, SiS Chip uses AHOLD to hold address bus of Pentium-like CPUs. While PCI master asserts PREQ#, SiS Chip will drive AHOLD firstly. And, if PCI master operates a peer-to-peer transaction, SiS Chip will deasserts AHOLD to permit CPU to do memory cycles concurrently. Otherwise, SiS Chip retains AHOLD signal until PREQ# is inactive and bus transaction completes.



Figure -2



Note: HOLD & HLDA are internal signals.

Figure -3

3. Target Initiated Termination

In general, SiS Chip is capable to complete all the requests to access main memory from PCI masters until master terminates the transaction actively. Sometimes, as SiS Chip is unable to respond or is unable to burst, it will initiate to terminate bus transactions and STOP# will be issued by doing Retry or Disconnect.

 

4. Target Retry

SiS Chip may operate Target Retry for one of two reasons:

1. Whenever a PCI master tries to access main memory and SiS Chip is locked previously by another agent, Target Retry will be signaled.

2. Once SiS Chip can‘t meet the requirement of target initial latency, Target Retry is used and no data is transferred.

 

5. Disconnect With Data

In some situations, such as the burst crosses a resource boundary or a resource conflict, SiS Chip might be temporarily unable to continue bursting, and, therefore, SiS Chip concludes an active termination.

1. SiS Chip supports PCI burst transfers, the bursting length can be 256 bytes, 512 bytes, 1K bytes, 2K bytes, or 4K bytes and depend on setting the register 80h bits[7:5] in Host to PCI bridge configuration space. A burst will be terminated by doing Disconnect if the transfer goes across the programmed bursting length. In this way, at most 128 cache lines of data can be uninterruptedly transferred no matter what the status they are in L1 and L2 cache. One reason for the constraint is that page miss may occur only once at the beginning of the entire bursting transaction since the maximum bursting length is always within the page size in any of the used DRAM.

2. If advanced snoop function is disabled, PCI transaction will not cross the cache boundary and also causes a Disconnect operation. Since the heavy overhead of inquiry cycles is not preventable, and SiS Chip can‘t keep bursting transfer.

 

6. Disconnect Without Data

If Target Subsequent Latency timer expires, it causes SiS Chip to assert STOP# by doing Disconnect operation.



Figure -4

7. DATA Flow

The major two data paths are PCI->PTHFF->DRAM and DRAM->CTPFF->PCI for PCI master write DRAM cycles and read DRAM cycles, respectively. For cache system, if an inquiry cycle hits Pipeline Burst SRAM, SiS Chip would read from L2 directly, but write DRAM and L2 CACHE simultaneously.

Based on snooping result, there are additional data path that SiS Chip should perform.

Table Data Flow Based on Snooping Result

PCI Master Read Memory Cycle
Result of Snoop
Status of L1	Status of L2	Data Flow	Operation
	Miss or None	DRAM -> CTPFF -> PCI	Read DRAM
Miss or Unmodified	Hit and Not Dirty	DRAM -> CTPFF -> PCI	Read DRAM
	Hit and Dirty	L2 -> CTPFF -> PCI	Read L2
	Miss or None	L1 -> CTMFF & CTPFF	Direct Read
		CTPFF -> PCI
Hit Modified	Hit, Dirty or Not	L1 -> L2 & CTPFF	Direct Read
		CTPFF -> PCI

 

PCI Master Write Memory Cycle
Result of Snoop
Status of L1	Status of L2	Data Flow	PSL Operation
	Miss or None	PCI -> PTHFF -> DRAM	Write DRAM
Miss or Unmodified	Hit, Dirty or Not	PCI -> PTHFF -> L2&DRAM	Write DRAM&L2
	Miss or None	L1 -> CTMFF
		PTHFF & CTMFF -> DRAM	Write Merge
Hit Modified	Hit, Dirty or Not	L1 -> L2
		PCI -> PTHFF -> L2&DRAM	Write DRAM&L2

Note: CTPFF means CPU-to-PCI Posted Write Buffer.

CTMFF means CPU-to-Memory Posted Write Buffer

PTMFF means PCI-to-Memory Posted Write Buffer

8. PCI Master Read/Write DRAM Cycle

If inquiry cycle hits neither L1 nor L2 cache, SiS Chip could perform prefetching/retiring operation and inquiry cycles simultaneously.



9. PCI Master Write L2 CACHE and DRAM Cycles

(1) Without Invalidation

For the purpose of writing L2 CACHE, PCI Slave controller (PSL) must drive the HBE[7:0]# and HD bus. Then, BOFF# is asserted to force CPU floats the host bus. And to retain the correct address on HA bus, advanced snoop is temporarily suspended.



Note: KHIT is an internal signal.

 

(2) With Invalidation



Note: KHIT is an internal signal.

 

10. PCI Arbiter

The main function of PCI arbiter takes charge of the PCI bus ownership assignment. This PCI arbiter supports at most 4 external PCI masters and 4 internal PCI masters. The arbitration operation is applied to the Host Bridge and CPU.

The arbitration scheme which we design is done at two layers. CPU has the highest priority, i.e., CPU will be the PCI bus owner if there is a request from the Host Bridge. If there is no request from the Host Bridge, rotational priority scheme will be applied to these masters.

 

Arbitration Algorithm

PCI Masters (Agent 0~6, SIO) Requests

Figure 3-5 shows the arbitration tree in arbiter design. Whenever a PCI cycle occurs, priority status will be changed. The initial priority for master 0-7 to own PCI bus is 4 -> 0->SIO->2->5->1->6->3->4.........



Figure -5 Arbitration Tree

NOTE: "SIO" means the System I/O for PCI to ISA bridge.

 

CPU Request

In our previous design, CPU will be constantly held if PCI masters continuously deliver requests to the arbiter. To address this problem in SiS Chip, we derived a timer-based algorithm to reserve PCI bandwidth for CPU. Three timers, PCI Grant Timer(PGT)/Master Latency Timer(MLT)/CPU Idle Timer(CIT), are included in the host bridge for this purpose.

Whenever the PCI bus is owned by any PCI device other than host bridge, PCI grant timer (PGT) starts to count. After the timer is expired, the host bridge asserts its request signal to ask for gaining the control of PCI bus. Since the host bridge has the highest priority, PCI arbiter grants the bus to the host bridge as soon as possible after it receives the request from the host bridge.

Once the host bridge get a chance to start a transaction on PCI bus, its master latency timer (MLT) begins to count. After MLT is expired, the host bridge deasserts its request signal to inform the arbiter that the host bridge no more needs the PCI bus. If there is any other PCI device that requests for the bus, arbiter grants the bus to the device and CPU is held again.

If there is no request from any PCI devices, the arbiter parks the bus on the host bridge. The ratio MLT/PGT approximately guarantees the minimum PCI bandwidth allocated to host bridge when CPU and PCI masters are contending for system resources, but it doesn’t constrain CPU’s highest utilization of PCI bus because of our bus parking policy.

To prevent the host bridge from capturing PCI bus too long while CPU actually has nothing to do at all, the third timer, CPU Idle Timer (CIT) is included in our design. CIT starts to count when the host bridge get a chance to start a transaction on PCI bus, but is reloaded with its initial value whenever the host bus leaves idle state. CIT actually keeps track on how long the CPU is in idle state. After CIT is expired, the host bridge deasserts its request signal just in the same manner as the case of MLT’s expiration.

PGT is a 16-bit timer. MLT and CIT are both 8-bit timers. All of the initial values of the three timers are programmable and can be tuned according to the nature of the application. Although CIT & MLT are both 8-bit timers, the initial value of CIT is typically programmed much smaller than MLT.

 

PCI peer-to-peer access concurrent with CPU to L2/DRAM access

With this feature, a transaction initiated by a PCI master targeting a PCI target won’t hold CPU. The CPU can still access L2 cache, system memory and PCI post-write buffers when PCI peer-to-peer activities are undergoing. With the enlarged 8 Dword deep PCI post-write buffers, it takes longer for CPU to halt while PCI peer-to-peer accesses are taking place.

 

Arbitration Parking

When no agent is currently using or requesting the bus, the arbiter will grant the bus ownership to the arbitration controller of SiS Chip.

 

CPU to PCI Bridge

The CPU to PCI bridge forwards the CPU cycles not targeting the local memory to the PCI bus, In the case of a 64-bit CPU request or a misaligned 32-bit CPU request, the bridge takes the duty of read assembly and write disassembly control, An 8 level post-write buffer is implemented to improve the performance of CPU to PCI memory write and CPU to IDE port write. Except for on-board memory write cycles, and any non-post write cycles forwarded to the PCI bus will be suspended until the post-write buffer is empty. For memory write cycles toward PCI or I/O write cycles towards IDE data port, the address and data from host bus are pushed into the post write buffer if it is not full. The push rate for a double word is 3 CPU clocks. The pushed data are, at later time, written to the PCI bus. If the addresses of consecutive written data are in double word incremental sequence and they are targeting memory space, they will be transferred to the PCI bus in a burst manner.

The bridge provides a mechanism for converting standard I/O cycles on the CPU bus to configuration cycles on the PCI bus. Configuration Mechanism#1 in PCI Specification is used to do the cycle conversion.

The bridge always intercepts the first interrupt acknowledge cycle from CPU bus, and forwards the second interrupt acknowledge cycle onto the PCI bus.

The bridge is designed to be able to handle asynchronous clock relationship between CPU and PCI. However, in order to enhance the performance of the bridge when PCI clock is lagging CPU clock by 2~4 ns, an optional synchronous mode is provided. The synchronous mode can averagely save two extra CPU clocks for a single non-post cycle.

8. Power Management Unit (PMU)

The function of PMU is to provide power management functions for the system to meet Green PC requirement. The main methodology of PMU is to generate SMI#, STPCLK# and FLUSH# signals to CPU for different situations. The PMU unit includes 3 major sub-blocks, Legacy PMU, APC and ACPI. Legacy PMU is the traditional PMU block and may be replaced by ACPI. APC(Auto Power Control) block is mainly responsible for the power supply control. For more information on APCI please refer to Section 3.6.8 Advanced Configuration and Power Interface (ACPI) on page *.The following sections will introduce the legacy PMU function.

 

1. Legacy PMU Block Diagram

Legacy PMU block can be divided into several sub-blocks as shown in Figure 3-6 Legacy PMU Block Diagram. Events Catching Logic is responsible for recording the events that request SMI#. Time Base generation logic is to generate the clock for timer. Timers are responsible for timeout reporting. SMI generation Logic is for SMI# generation. STPCLK# generation Logic is for STPCLK# generation. FLUSH# generation Logic is for FLUSH# generation.



Figure -6 Legacy PMU Block Diagram

 

2. Time Base Generation Logic

All the clocks used in Legacy PMU timers are derived from 14.318 MHZ clock. To support different time slots, SiS Chip uses frequency divider to obtain the clock we require. The time slots SiS Chip support are divided in two classes. One is for monitor standby timer and the other is for system standby timer. The former includes 6.6sec, 0.84sec, 13.3ms and 1.6ms programmability in register 96h bits[7:6] of Host-to-PCI bridge configuration space while the latter includes 9 sec, 1.1 sec, 70ms and 8.85ms programmability in register 91h bits[1:0] of Host-to-PCI bridge configuration space. Besides, SiS Chip provide CPU clock for timer in test mode.

 

3. Timers

There are three kinds of timer defined in Legacy PMU. One is for monitor activity, another is for system activity and the other is for STPCLK# behavior generation. In order to save monitor power dissipation, we provide monitor standby timer to detect if there is any monitor-related activity. If there is any activity, monitor standby timer will be reloaded. Otherwise, monitor standby timer will continuously count down. If it count to zero, it will report timeout event. System standby timer has the same operation as monitor standby timer. STPCLK# assertion/deassertion timer is to toggle STPCLK# signal in Throttling mode.

 

4. Event Catching Logic

System Sleep Events

The timeout of system timer will request SMI# to enter Sleep state. If throttling mode is enabled, Legacy PMU will enter throttling mode. Otherwise, if STPCLK# mode is enabled, Legacy PMU will enter sleep mode. If both modes are disabled, Legacy PMU remains wakeup.

 

System Wakeup events

The following events will wakeup system from Standby state to Normal state.

Software Wakeup

RING

IRQ 1-15, NMI

INIT

PCI or ISA master request

 

Monitor Timeout event

If monitor timer expired, SMI# will be generated for the request of turn-off monitor power.

 

Monitor Wakeup Events

The following shows the events that can wakeup monitor from Standby to Normal state.

IRQ1-15,NMI

PCI master, ISA master activity

Ring Activity

 

SMI Sources

The following shows the sources to generate SMI request.

System Standby SMI

System Wakeup SMI

Throttling Wakeup SMI

Monitor Standby SMI

Monitor Wakeup SMI

Ring SMI

Keyboard Port SMI

Primary Hard Disk Port SMI

Secondary Hard Disk Port SMI

Primary Serial Port SMI

Secondary Serial Port SMI

Parallel Port SMI

APM SMI

Break Switch SMI (External SMI)

10-bit Programmable Port SMI

16-bit Programmable Port SMI

IRQ SMI

USB SMI

 

5. Output generation Logic

SMI# generation

When there is any event to request entering sleep/throttling/wakeup state, SMI# will be issued. When SMI# is recognized by CPU, SMI routine will handle the operation of state transition.

 

STPCLK# generation

STPCLK# generation is initialized by SMI sub-routine by writing Reg. 93 bit 3 to ‘1’ in Host to PCI bridge configuration space. The behavior of STPCLK# depends on the configuration register setting, i.e., non-throttling or throttling.

 

FLUSH# generation

FLUSH# is generated for DeTurbo mode. By issuing FLUSH#, CPU will write back all modified cachelines in the data cache and invalidate both internal code and data caches. Flush Acknowledge special cycle will be driven once flush operation is completed. Hence, CPU performance can be degraded.

 

6. Operation of Power Management

There are three states in PMU, i.e., Wakeup state, Sleep state and Throttling state. In wakeup state, system wakes up from sleep or throttling state. In sleep state, STPCLK# will always asserted until exiting Sleep state. In throttling state, STPCLK# will be asserted and deasserted periodically.

Once CPU recognizes a STPCLK# interrupt, CPU will perform the following:

1. Wait for all instructions being executed to complete.

2. Flush the instruction pipeline of any instructions waiting to be executed.

3. Wait for all pending bus cycles to complete and EWBE# to go active.

4. Drive a special bus cycle(stop grant bus cycle) to indicate that the clock is being stopped. Stop grant bus cycle is decoded as follows: M/IO#=0, D/C#=0, W/R#=1, Address Bus=00000010H (A4=1), BE7#-BE0#=11111011, Data bus=undefined.

5. Enter low power mode.

The rising edge of STPCLK# indicates that CPU can return to program execution at the instruction following the interrupted instruction

 

7. Hardware Limitation

If STPCLK# is configured as throttling mode. There is a possibility for SMI to break Configuration Register Access. To elaborate, there are two steps to access Configuration registers. The first step is to program I/O port CF8h and the second one is to program I/O port CFCh. If SMI routine begins to be executed between the two steps by CPU. There is possibility for PMU to cause mal-function.

The recommended solution for this problem is to read the CF8h data before executing other code in SMI routine and write back the data to CF8h before exiting SMI routine.

 

9. PCI/ISA System I/O (PSIO)

1. Functional Description

As a PCI slave device, PSIO responds to both I/O and memory transfers. PSIO always target-terminates after the first data phase for any bursting cycle.

The PSIO is assigned as the subtractive decoder in the Bus 0 of the PCI/ISA system by accepting all accesses not positively decoded by some other agent. In reality, the PSIO only subtractively responds to low 64K I/O or low 16M memory accesses. PSIO also positively decodes I/O addresses for internal registers, and BIOS memory space by asserting DEVSEL# signal on the medium timing.

As a PCI master device, the PCI master bridge on behalf of DMA devices or ISA Master devices start to drive the AD bus, C/BE[3:0]# and PAR signals. When MEMR# or MEMW# is asserted, the PSIO will generate FRAME#, and IRDY# to PCI bus if the targeted memory is not on the ISA side. The valid address and command are driven during the address phase, and PAR signal is asserted one clock after that phase. PSIO always activated FRAME# for 2 PCLKs because it does not conduct any bursting cycle.

The ISA address decoder is used to determine the destination of ISA master devices or DMA devices. This decoder provides the following options as they are defined in registers 48h to 4Bh of PCI to ISA Bridge configuration space.

a. Memory: 0-512K

b. Memory: 512K-640K

c. Memory: 640K-768K(video buffer)

d. Memory: 768K-896K in eight 16K sections(Expansion ROM)

e. Memory: 896K-960K(lower BIOS area)

f. Memory: 1M-XM-16M within which a hole can be opened. Access to the hole is not forwarded to PCI bus.

g. Memory:>16M automatically forwards to PCI.

 

 

2. ISA Bus Controller

The SiS Chip’s ISA Bus Interface accepts those cycles from PCI bus interface and then translates them onto the ISA bus. It also requests the PCI master bridge to generate PCI cycle on behalf of DMA or ISA master devices. The ISA bus interface thus contains a standard ISA Bus Controller (IBC) and a Data Buffering logic. IBC provides all the ISA control, such as ISA command generation, I/O recovery control, wait-state insertion, and data buffer steering. The PCI to/from ISA address and data bus bufferings are also all integrated in SiS Chip. The SiS Chip can directly support 4 ISA slots without external data or address buffering.

Standard ISA bus refresh is requested by Counter 1, and then performed via the IBC. IBC generates the pertinent command and refreshes address to the ISA bus. Since the ISA refresh is transparent to the PCI bus and the DMA cycle, an arbiter is employed to resolve the possible conflicts among PCI cycles, refresh cycles, and DMA cycles.

 

3. DMA Controller

The SiS Chip contains a seven-channel DMA controller. The channel 0 to 3 is for 8-bit DMA devices while channel 5 to 7 is for 16-bit devices. The channels can also be programmed for any of the four transfer modes, which include single, demand, block, and cascade. Except in cascade mode, each of the three active transfer modes can perform three different types of transfers, which include read, write, and verify. The address generation circuitry in SiS Chip can only support 24-bit address for DMA devices.

 

Distributed DMA

Distributed DMA allows the individual DMA channels to be separated into different physical devices on the PCI bus. In distributed DMA, the DMA Master contains the addresses that were occupied by the traditional ISA DMA Controller(8237). This device will respond to any system read or write to the traditional ISA DMA address locations so the software will continue to think it is communicating with a standard DMA controller. The SiS Chip is the DMA Master and the protocol is as follows:

1). When the CPU bridge attempts to read/write a legacy DMA register, a PCI I/O cycle will be initiated on the PCI bus with a legacy DMA address. The SiS Chip will take control of this cycle by driving DEVSEL# active, driving the internal Request(requesting the PCI bus), and issuing a PCI retry to terminate this cycle.

2). When granted the PCI bus, the SiS Chip will run up to PCI I/O byte read/writes. The specific I/O addresses for each legacy DMA address are remappable. The purpose of these read/writes is to return/send the individual channel read/write information. DMA Slave devices must only respond to the slave address assigned to them and not any legacy DMA address.

3). At the end of the last read/write the SiS Chip will set an internal flag indicating completion and will drive its internal Request inactive (relinquishing the PCI bus) and wait for the retried PCI I/O read/write from the CPU bridge.

4). The PCI I/O read/write will be retried. If it was a read, theSiS Chip will return the data. If it was a write, the SiS Chip will simply terminate the cycle. Then the SiS Chip will reset the internal flag.

 

4. Interrupt Controller

The SiS Chip provides an ISA compatible interrupt controller that incorporates the functionality of two 82C59 interrupt controllers. The two controllers are cascaded so that 14 external and two internal interrupts are supported. The master interrupt controller provides IRQ<7:0> and the slave one provides IRQ<15:8>. The two internal interrupt are used for internal functions only and are not available externally. IRQ2 is used to cascade the two controllers together and IRQ0 is used as a system timer interrupt and is tied to interval Counter 0. The remaining 14 interrupt lines are available for external system interrupts.

Priority	Label	Controller	Typical Interrupt Source
1	IRQ0	1	Timer/Counter 0 Out
2	IRQ1	1	Keyboard
3-10	IRQ2	1	Interrupt from Controller 2
3	IRQ8#	2	Real Time Clock
4	IRQ9	2	Expansion bus pin B04
5	IRQ10	2	Expansion bus pin D03
6	IRQ11	2	Expansion bus pin D04
7	IRQ12	2	Expansion bus pin D05
8	IRQ13	2	Coprocessor Error Ferr#
9	IRQ14	2	Fixed Disk Drive Controller Expansion bus pin D07
10	IRQ15	2	Expansion bus pin D06
11	IRQ3	1	Serial port 2, Expansion Bus B25
12	IRQ4	1	Serial port 1, Expansion Bus B24
13	IRQ5	1	Parallel Port 2, Expansion Bus B23
14	IRQ6	1	Diskette Controller, Expansion Bus B22
15	IRQ7	1	Parallel Port1, Expansion Bus B21

In addition to the ISA features, the ability to do interrupt sharing is included. Two registers located at 4D0h and 4D1h are defined to allow edge or level sense selection to be made on an individual channel by channel basis instead of on a complete bank of channels. Note that the default of IRQ0, IRQ1, IRQ2, IRQ8# and IRQ13 is edge sensitive, and can not be programmed. Also, each PCI Interrupt(INTx#) can be programmed independently to route to one of the eleven ISA compatible interrupts(IRQ<7:3>, IRQ<15:14>, and IRQ<12:9>) through PCI to ISA bridge configuration registers 41h to 44h.

 

Serial IRQ

The Serial IRQ provides a mechanism for communicating IRQ status between ISA legacy components, PCI components, and PCI system controllers. A serial interface is specified that provides a means for transferring IRQ and/or other information from one system component to a system host controller. A transfer, called an serial IRQ cycle, consists of three frame types: one Start Frame, several IRQ/Data Frames, and one Stop Frame. This protocol uses the PCI clock as its clock source and conforms to the PCI bus electrical specification.

 

Timing Diagrams For Serial IRQ Cycle.



Figure -7 Start Frame timing with source sampled a low pulse on SMI#

 



Figure -8 Stop Frame Timing with Host using 17 SIRQ# sampling period

 

Serial IRQ Cycle Control

There are two modes of operations for the serial IRQ start frame.

a) Quiet(Active) Mode: Any device may initiate a Start Frame by driving SIRQ# low for one clock, while SIRQ# is Idle. After driving low one clock the SIRQ# must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SIRQ# is Active. The SIRQ# is Idle between Stop and Start Frames. This mode of operation allows the SIRQ# to be Idle when there are no IRQ/Data transitions which should be most of the time.

Once a Start Frame has been initiated the SiS Chip will take over driving the SIRQ# low in the next clock and will continue driving the SIRQ# low for a programmable period of three to seven clocks more. This makes a total low pulse width of four to eight clocks. Finally, SiS Chip will drive the SIRQ# back high for one clock, then tri-state.

Any serial IRQ device which detects any transition on an SIRQ# line for which it is responsible must initiate a Start Frame in order to update the SiS Chip unless the SIRQ# is already in a serial IRQ cycle and the IRQ/Data transition can be delivered in the serial IRQ cycle.

b) Continuous(Idle) Mode: Only the SiS Chip can initiate a Start Frame to update SIRQ# line information. All other serial IRQ agents become passive may not initiate a Start Frame. SIRQ# will be driven low for four to eight clocks by the SiS Chip . This mode has two functions. It can be used to stop or idle the SIRQ# or the SiS Chip can operate SIRQ# in a continuous mode by initiating a Start Frame at the end of every Stop Frame. A serial IRQ mode transition can only occurs during the Stop Frame. Upon reset, the Serial IRQ bus is default to Continuous mode, therefore only the SiS Chip can initiate the first Start Frame. Slave must continuously sample the Stop Frames pulse width to determine the next serial IRQ cycle's mode.

 

IRQ/Data Frame

Once a Start Frame has been initiated, all serial IRQ devices must detect for the rising edges of the Start pulse and start counting IRQ/Data Frames from there. There are three clock phases for each IRQ/Data Frame:Sample phase, Recovery Phase, and Turn-around phase. During the Sample phase the serial IRQ device must drive the SIRQ# low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SIRQ# must be left tri-stated. During the Recovery phase , a serial IRQ device will drive SIRQ# back high if it has driven the SIRQ# low in the previous clock. During the Turn-around phase all serial IRQ devices must be tri-stated. All serial IRQ devices will drive SIRQ# low at the appropriate sample point regardless of which device initiated the sample activity, if its associated IRQ/Data line is low.

The Sample phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one.(e.g. the IRQ5 sample clock is the sixth IRQ/Data frame, (6x3)-1=17th clock after the rising edge of the Start Pulse).

Serial IRQ Sampling Periods
IRQ/Data Frame	Signal Sampled	# of clocks past Start
2:1	Reserved	2
3	SMI#	8
4	IRQ3	11
5	IRQ4	14
6	IRQ5	17
7	IRQ6	20
8	IRQ7	23
9	IRQ8#	26
10	IRQ9	29
11	IRQ10	32
12	IRQ11	35
13	IRQ12	38
14	IRQ13	41
15	IRQ14	44
16	IRQ15	47
17	IOCHCK#	50
21:18	Reserved	53
32:22	Unassigned	95

At the end of each Sample phase, the SiS Chip will sample the state the SIRQ# line and replicate the status the original IRQ/Data line at the input to the 8259s Interrupt Controller.

 

Stop Cycle Control

Once all IRQ/Data frames have completed, the SiS Chip will terminate SIRQ# activity by driving Stop cycle. Only the SiS Chip can initiate the stop frame. A Stop Frame is indicated by the SiS Chip driving SIRQ# low for two clocks(Quiet Mode) or 3 clocks(Continuous Mode), then back high for one clock. In the Quiet mode, any serial IRQ device may initiate a Start frame in the third clock or more after the rising edge of the Stop frame pulse. In the Continuous mode, only the SiS Chip may initiate a Start frame in the third clock or more after the rising edge of the Stop frame pulse.

 

EOI/ISR Latency

When a legacy interrupt is deasserted, it will start a serial interrupt frame. An EOI can occur after the legacy interrupt is deasserted, however, the 8259 may not detect the deasserted interrupt because it is still being serialized. This could cause the 8259 to generate interrupt as soon as the EOI is received. By delaying EOIs and ISR read to the 8259 in order to ensure that these latency issues are well covered. Note that, EOI indicates the End of Interrupt and ISR indicates the Interrupt Service Routine.

 

5. Timer/Counter

The SiS Chip contains 3 channel counter/timer that is equivalent to those found in the 82C54 programmable interval timer. The counters use a division of 14.318MHz OSC input as the clock source. The outputs of the timers are directed to key system functions. Counter 0 is connected to the interrupt controller IRQ0 and provides a system timer interrupt for a time-of-day, diskette time-out, or the other system timing function. Counter 1 generates a refresh-request signal and Counter 2 generates the tone for the speaker.

 

6. Integrated Real Time Clock (RTC)

Real Time Clock Module

The Real Time Clock module in the SiS Chip contain the industrial standard Real Time Clock which is compatible to MC146818, and the Auto Power Control circuitry mainly to support the ACPI power control functions. The Real Time Clock part provides a time-of-day clock with alarm and one hundred year calendar, a programmable periodic interrupt, 114 Bytes of standard CMOS SRAM, and 128 Byes of extended CMOS SRAM. The Auto Power Control part provides the software/hardware power up/down functions. Figure 3-9 shows the block diagram of the RTC module.



Figure -9 RTC module Block Diagram

 

RTC Registers & RAM

Three separate RTC registers & RAMs are provided in the SiS Chip. One is called the Standard Bank, another is the Extended Bank, and the other is the APC (Auto Power Control) registers. All of these registers are referenced through the same index, and data port, ie. port 70H and 71H, respectively. The access control with which that the three portions of registers are appropriately addressed are stored in PCI-ISA:45h[3] (EXTEND_EN bit) and PCI-ISA:44h[4] (APCREG_EN bit). EXTEND_EN bit enables the access of the Standard Bank while it is 0. The EXTEND_EN bit must be programmed to 1 to read/write the Extended Bank. The APCREG_EN bit toggle the 70H/71H access between the RTC registers and APC registers. The 70H/71H port will access the RTC Standard/Extended Bank if APCREG_EN bit is 0. The 70H/71H port will access the APC register if APCREG_EN bit is 1. Figure 3-10 shows the address map of the Standard Bank. In the Standard Bank, the lower 10 bytes contain the time, calendar, and alarm data. The registers Ah,Bh,Ch, and Dh contain the control and status bytes. The last two bytes (7Eh, 7Fh) are the Day of Month Alarm byte and the Month Alarm byte which are the extended alarm features requested by the ACPI. The Day of the Month Alarm selects the day within the month to generate a RTC alarm while the Month Alarm selects the month within the year to generate a RTC alarm. The remain 112 bytes in the Standard Bank are the general purpose RAM bytes. In the Extended Bank, another 128 bytes are also provided for the general purpose usage.



Figure -10 Address Map of the Standard Bank

The APC registers are provided to support the Auto Power Control Function. The register 02H defines the "Day of the Week" Alarm byte which can select the day within a week to generate a RTC alarm. The 03H, 04H registers contain the control information for the auto power control functions. Figure 3-11 shows the address map of the APC registers.

Address	Register Name
00h	Reserved
01h	Reserved
02h	Day of Week Alarm
03h	Auto Power Control Register I
04h	Auto Power Control Register II

Figure -11 Address Map of the APC Control Register

RTC Update Cycle

The primary function of the the update cycle is to increment the seconds bytes, the minutes bytes and so forth through to the year of the century byte. The update cycle also compares each alarm byte in the corresponding time byte and issues an alarm if a match or if a "Don’t care" code(11XXXXXX) is present in this time byte. Figure 3-12 shows the block diagram of the RTC.



Figure -12 Block Diagram of RTC

 

RTC External Connection Requirement

The SiS Chip‘s RTC is powered by the RTCVDD, & RTCVSS. In reality, not only the internal circuitry of the RTC, the pins associated with the RTC module are also powered by the specific power planes. They are ONCTL#, PWRGD, PSRSTB#, SWITCH, PWRBT#, RING, OSCI, OSCO, GPIO5, and GPIO10.

SiS Chip is designed to support the 3V output with 5V input tolerant I/O buffers. The 5V tolerant capability is achieved by two 5V power pins(VCC5) sustaining the I/O associated well. The two pins must be connected to VCC5 if 5V input tolerance is required. The Ball NO. of these two pins are AF15, AB2 in SiS5597 and D15, H2 in SiS5598.

Please note that the RTC-related ten pins have no 5V tolerance since the associated well for the RTC is powered by the RTCVDD. The voltage level of RTCVDD is not allowed to be higher than 3.3V since SiS Chip employs the 3.3V process. Thus, DO NOT POWER THE RTCVDD HIGHER THAN 3.3V. Please ensure the ten pins related to the RTC follows this requirment. For instance, a voltage divider is requiried to clamp the PWRGD from the power supply to around 3.3V. These ten pins are : ONCTL#, RING, PWRGD, PSRSTB#, OSCI, OSCO, SWITCH, PWRBT#, GPIO5, GPIO10.

SiS Chip contains 3 wells if categorized by the driving power:

1) the internal circuitry excluding the RTC (powered by 3.3V OVDD)

2) the RTC(powered by RTCVDD), and

3) the I/O buffers(powered by 5V VCC5).

 

7. Auto Power Controller

1. ACPI Extended Alarm Function: The ACPI Extended Alarm Function can set the alarm by the day within a month or the month within a year. The Day of the Month and the Month Alarms bytes are stored in the register 7Eh and 7Fh of RTC Standard Bank. To enable this function the APC_EN bit in APC Register I must be enabled.
2. Day of Month Alarm Function: The Day of Month Alarm Function can set the alarm by the day within a week. With this additional feature, the SiS Chip allows the system to be alarmed up on, say, each Monday 08:00. The Day of the Week Alarm byte is located in the register 2h of the APC registers. Note that this feature is enabled when DayWeekAlarm_EN bit located in the bit 0 of the Day of the Week Alarm Register, and the APC_EN bit are both set. ACPI extended alarm function is the default alarm mode once the APC_EN bit is set. However, the ACPI extended alarm mode is replaced by the Day of the Week alarm mode once the DayWeekAlarm_EN bit is set.

4. SiS chip supplies a special pin, GPIO10/ACPILED, to facilitate the Green PC denote-LED design. If this pin is in its output mode (APC II[3] = 0), and pin definition is ACPILED (APC II[1] = 1), and 1 Hz Function Support is enabled (APC II[0] = 1), and ACPI function is enabled (PCI to ISA:40h[7] = 1), then SiS chip will send out an 1 Hz signal on this pin to turn on/off the external LED whenever GPIO10 pin status register (ACPI:18h[10]) is set to 1.

1. Advanced Configuration and Power Interface (ACPI)

Name	Address	Register Description
PM1a_STS	00h	Power Management 1a Status Register
PM1b_STS	01h	Power Management 1b Status Register
PM1a_EN	02h	Power Management 1a Enable Register
PM1b_EN	03h	Power Management 1b Enable Register
PM1a_CNT	04h	Power Management 1a Control Register
PM1b_CNT	05h	Power Management 1b Control Register
PM_TMR	08h	Power Management Timer
P_CNT	0Ch	Processor Control
P_LVL2	10h	Processor LVL2 Register
P_LVL3	11h	Processor LVL3 register
PM2_CNT	12h	Power Management 2 Control
GP_TMR	13h	General Purpose Timer Register
GPIO_STS1	14h	Status register 1 for general purpose I/O pins
GPIO_STS2	15h	Status register 2 for general purpose I/O pins
GPIO_EN1	16h	Enable register 1 for general purpose I/O pins
GPIO_EN2	17h	Enable register 2 for general purpose I/O pins
GPIO_CNT1	18h	Control/Read back status register 1 for general purpose I/O pins
GPIO_CNT2	19h	Control/Read back status register 1 for general purpose I/O pins
GPIO_SEL1	1Ah	Input/Output Selection register 1 for general purpose I/O pins
GPIO_SEL2	1Bh	Input/Output Selection register 2 for general purpose I/O pins
GPIO_MUX1	1Ch	GPIO Mux. function selection register 1
GPIO_MUX2	1Dh	GPIO Mux function selection register 2
GPIO_LVL1	1Eh	Polarity selection register 1 for general purpose I/O pins
GPIO_LVL2	1Fh	Polarity selection register 2 for general purpose I/O pins
SMI_CMD	20h	SMI command port
MUX_REG	24h	Mux. function selection register
AUX_STS	25h	Auxiliary Control Status register
AUX_EN	26h	Auxiliary Control Enable register
SMI_PEN	28h	Programmable SMI command port enable value
SMI_PDIS	29h	Programmable SMI command port disable value
SMI_REG	2Ah	Scratch register for SMI or ACPI use
ACPI_TST	2Bh	APCI test mode register

1. Integrated PCI Master/Slave IDE Controller

Old Definition	New Definition
IIOW#	STOP#
IIOR#	HDMARDY# --- data in operation HSTROBE --- data out operation
ICHRDY#	DSTROBE --- data in operation DDMARDY# --- data out operation

1. As a sender during data-out operation and the internal FIFO is empty. The burst will resume after the DMA engine re-fill the FIFO with data from system memory.
2. As a receiver during data-in operation and the internal FIFO is full. The burst will resume after the DMA engine dump the data in FIFO to system memory.
3. For a PRD table with multiple entries, the DMA engine will start the burst data transfer after base address and byte-count of one entry is read. When the data transfer for the current entry is completed and the next entry has not yet been read into the controller, the SiS Chip shall also initiate a pause. After the base address and byte-count for next entry is read, the burst resumes.

1. During the burst data transfer, the host(CPU) is trying to access the command/control block registers. Since the command/control block access cycle is assigned to have higher priority than data transfer cycles, the SiS Chip must first terminate the burst, de-asserts the IDACK# signal, generate the corresponding DA[2:0] and CS[1:0] on IDE bus, and then complete the command/control block register access cycle. After that, the burst can be resumed by entering the Burst Initiation phase when the device re-asserts IDREQ.
2. Since the usage of the IDE/ISA bus is arbitrated among PCI-to-ISA cycle, ISA masters and IDE controllers. Once the PCI-to-ISA cycle or the ISA masters gains higher priority on the bus and need to access the ISA bus, the IDE controller must yield. In such cases, when Ultra-DMA mode is operating, the controller will initiate a burst termination. After the preempting cycles are finished, the Ultra-DMA burst can be resumed.

2. Delayed Transaction

Delayed transaction is a mechanism used when the target, like PCI-to-ISA bridge in SiS Chip on behalf of the ISA devices, cannot complete the transaction within the initial latency of 16 PCI clocks. To support delayed transaction function, the PCI-to-ISA bridge would latch all the information required to complete the transaction and then terminate the master with a retry. The PCI-to-ISA bridge will then translate the request into ISA cycle to obtain the requested data for a read transaction or complete the actual request if a write request. During this period the original master would keep retrying the cycles while other PCI masters are also allowed to use the bus that would normally be wasted holding the original master in wait states. Eventually, the original master would get the latched data for read transaction, or complete the cycle for the write transaction when the PCI-to-ISA bridge completes the ISA cycles.

 

Delayed Transaction and ISA Master Cycle Arbitration

ISA devices or DMA controller embedded in the PCI-to-ISA bridge of SiS Chip may become ISA master and initiate cycles to access PCI bus. It is quite often that the ISA master may request for ISA bus while there is a delayed transaction undergoing. As a result, an arbitration rule is adopted in the PCI-to-ISA bridge to prevent conflict on the ISA bus. In this section, we will first describe the actions of an ISA master cycle, and next outline the arbitration rules. For convenience, the progress of a delayed transaction cycle will be divided into three phases: DT_PH_1, DT_PH_2 and DT_PH_3.



 

DT_PH_1: This is the period when there is no pending delayed transaction in progress

DT_PH_2: This is the period when the ISA cycle corresponding to the delayed transaction is undergoing on ISA bus.

DT_PH_3: From the end of ISA cycle up to the original PCI master successfully retries and completes the whole delayed transaction.

Note: the delayed transaction is said to be pending during DT_PH_2 and DT_PH_3.

Traditionally, ISA(DMA) masters request ISA bus by asserting their corresponding DREQs to DMA controller embedded in the PCI-to-ISA bridge. The PCI-to-ISA bridge, in turn, will generate PHOLD# to system arbiter to request for PCI bus. The PHOLD# will be asserted as long as DREQ is asserted by the ISA master. In response to PHOLD#, the system arbiter grants PCI bus to PCI-to-ISA bridge by asserting PHLDA#. The PCI-to-ISA bridge, upon receiving PHLDA#, will first check if ISA bus is busy or idle. If busy, it will defer the assertion of DACK# until ISA bus returns to idle. If idle, it will assert the corresponding DACK# immediately to inform ISA master to start. ISA master when received DACK#, can then start its cycles transferring data to or from PCI(ISA) bus. When ISA master finishes its cycles, it de-asserts DREQ and then PHOLD# will also be de-asserted immediately. The system arbiter, in response to the desertion of PHOLD#, will immediately de-assert PHLDA#. This completes the whole sequence of ISA master cycles.

Note: PHOLD# and PHLDA#, in SiS Chip, are internal signals interfaced between the system arbiter and the PCI-to-ISA bridge.

 

Delayed Transaction and ISA Master Arbitration Rule

1. When ISA master issues DREQ and there is no pending delayed transaction, this is the normal case that no arbitration is needed and the PCI-to-ISA bridge behaves exactly as that stated above.

2. When ISA master issues DREQ and there is currently a delayed transaction pending, the PCI-to-ISA bridge will disregard the pending delayed transaction and immediately generate PHOLD# to request for PCI bus.

3. When the system arbiter grants PCI bus to ISA master by asserting PHLDA#, and the delayed transaction is in DT_PH_2, i.e., the ISA bus is busy, the PCI-to-ISA bridge should defer the assertion of DACK# until DT_PH_3 is entered. Otherwise, ISA master will start its cycles as soon as DACK# is asserted and may result in ISA bus conflict.

4. If PHLDA# is asserted when the pending delayed transaction is already in DT_PH_3, ie., the ISA bus has returned to idle, the PCI-to-ISA bridge can assert DACK# immediately and hence ISA master may start its cycles even when the delayed transaction is not yet completed on PCI bus.

5. During the period that ISA master is active and delayed transaction is pending in DT_PH_3, the original PCI master that initiated the dalayed transaction will temporarily stop retrying on the PCI bus because PCI bus is now owned by ISA master.

6. After the ISA master finishes its data transfers, the original PCI master should eventually re-gain PCI bus and retry successfully.

4. The Architecture of ISA/IDE Multiplexed bus

SiS Chip interfaces to IDE bus and ISA bus through multiplexed pins. The data bus IDA[15:0] of IDE channel_0 share pins with SD[15:0] of ISA bus, while the data bus IDEB[15:0] of IDE channel_1 share pins with LA[23:17] and SA[16:8] of ISA bus. The resulting bus architecture interfaced with SiS Chip will be called IDE/ISA bus. The pin-sharing imposes limitation on the IDE/ISA bus such that IDE and ISA can not be operating simultaneously. As a result, when either of the IDE channels is operating, the ISA bus activities must be idle. Conversely, when the ISA bus is used by the PCI-to-ISA bridge or ISA masters, both the IDE channels must not be operating. There are two exceptions that ISA and IDE can both be operating. One is ISA refresh cycle initiated by refresh controller embedded in SiS Chip. Since only SA[7:0] and MEMR# are used during refresh cycles, it is apparent there will be no conflict between ISA and IDE. The other exception is when the internal registers of legacy ISA bus controllers (8259, 8237, 8254) are being accessed. These registers located inside the SiS Chip and hence no external AT cycles will be generated when they are being accessed. Therefore, these registers can be accessed when IDE is operating.

The IDE bus signals are driven directly by the chip, while the ISA bus signals are further buffered by 74LS245s. Two 74LS245 are used to interfaced with ISA address signals and two 74LS245 are used to interfaced with ISA data signals. The MR16# signal of ISA is used to control the direction of address signals to or from ISA slots. When a ISA master gains ISA bus ownership by asserting MR16#, the direction of address is from ISA to IDE. In all other cases, the direction of address is from IDE to ISA. During ISA refresh cycles, the ENABLE pins of the two 74LS245s interfaced with address signals are disabled by the RFH# signal such that ISA address signals will not appear on IDE and hence IDE operations will not be affected.

The SDOEL and SDOEH signals connect to the DIR pins of 74LS245s and are used to control the direction of ISA data flow. SDOEL is used to control low-byte, and SDOEH is used to control high-byte. When the two signals are high, the direction of ISA data flow is from IDE to ISA. When the two signals are low, the direction of ISA data flow is from ISA to IDE. When either of the IDE channels is operating, the SDOEL and SDOEH will be both high such that the data direction is from IDE to ISA. When PCI-to-ISA bridge or ISA master is active, SDOEL and SDOEH will be depending on the read/write status of the current transaction.

The above mechanism assumes that ISA devices located on ISA slots will not be affected by IDE signals propagate through the 74LS245s and appear on ISA address/data buses when IDE is operating, since the DIR signals will park the 74LS245s in the IDE-to-ISA direction.

To arbitrate the IDE and ISA bus, SiS Chip has developed an arbitration scheme on the IDE/ISA bus. By taking advantage of the arbitration scheme, IDE controller and ISA devices can each get a fair share of bus usage. The arbitration scheme will be described in the following section.

 

 

 

 

IDE/ISA Bus Limitation

1. The two IDE channels are fully separated and hence can be operating simultaneously without intervening each other.

2. Due to the limitation of multiplexed pins, when any one of the IDE channel is busy, ISA bus activities must remain idle. Conversely, when the ISA bus is busy, the two IDE channels must be idle.

There are three candidates compete for the IDE/ISA bus

1. PCI-to-ISA cycle

2. ISA master

3. IDE controllers (of the two channels)

 

Basic Rules

1. PCI-to-ISA cycle can preempt IDE cycles immediately

2. ISA master cycles cannot be preempted

3. A simple rotating-priority is adopted for IDE controllers and ISA masters

4. The minimum bandwidth of IDE controller can be guaranteed by programming the minimum accessed time register(50h~51h) in PCI IDE configuration space.

5. ISA master can preempt IDE controller only when its priority is larger than both IDE channels.

 

Arbitration Scheme

1. Since the PCI-to-ISA cycle and ISA master are already arbitrated by the system arbiter of SiS Chip, it is for sure that they will never be active simultaneously. Therefore, the IDE/ISA arbitration scheme can rule out this possibility.

2. PCI-to-ISA cycle can interrupt IDE controller immediately. When IDE controller of either channels detects a PCI-to-ISA cycle is requesting at the PCI-to-ISA bridge, it should suspend its operation immediately by completing the current IDE cycle. If in DMA mode, it should also deassert DACK#. The IDE controller should remain in idle state until the PCI-to-ISA cycle is complete and then resume its operation. The PCI-to-ISA bridge, on the other hand, should temporarily retry the PCI-to-ISA cycle on PCI bus when any one of the IDE channel is busy. It keeps retrying the cycle until both IDE channels are in idle state. It is obvious that this rule favors PCI-to-ISA cycles because IDE multi-sector data transfers are quite often and may last for a long period of time. If the PCI-to-ISA cycle can not preempt IDE, it may be waiting too long and result in system failure.

3. ISA master cycles cannot be suspended and then resumed later. Once the ISA master was granted to initiate its cycles, it must complete the whole process without being interrupted.

4. To solve the arbitration between IDE and ISA master, a rotating priority scheme is adopted to ensure each of the candidates will get a fair share of bus usage.

Since the ISA master can not be preempted, it can hold the bus as long as it desires. It is likely that IDE channels will not be able to get a fair share of bus usage when ISA master is heavily transferring data. As a supplement, the minimum accessed time for IDE channels can be guaranteed by programming the minimum accessed time register. This 16-bit register defines a minimum accessed time in terms of PCI clock for IDE. Every IDE data transfer is guaranteed not to be preempted by ISA master before IDE has used the bus for this amount of time. As such, the minimum bandwidth of IDE channels can be guaranteed. To count the amount of time that the bus is used by IDE, there is a granting timer associated with each IDE channel counting with PCI clock. Initially, the granting timer is loaded with the value of the minimum accessed time register. For every PCI clock, if the IDE/ISA bus is used by the associated IDE channel, the granting timer should count-down once. When the timer expires and ISA master is requesting for bus, the IDE channel should suspend its cycles and yield the bus to ISA master. The granting timer can be reloaded when ISA master finish using the bus.

Define:

PRIO_ISAM: the priority of ISA master

PRIO_IDE0: the priority of IDE channel_0

PRIO_IDE1: the priority of IDE channel_1

Operation rules for the rotating priority scheme:

· PRIO_ISAM will be the lowest when ISA master finishes its data transfer cycles.

· PRIO_IDE0 will be the lowest when the granting timer of IDE channel_0 expired

· PRIO_IDE1 will be the lowest when the granting timer of IDE channel_1 expired.

· ISA master can only preempt both IDE cycles when

PRIO_ISAM> PRIO_IDE0 and PRIO_ISAM> PRIO_IDE1

Consider the following sequence of events as an example.

Initially, after the system is reset:

PRIO_ISAM > PRIO_IDE0 and PRIO_ISAM > PRIO_IDE1

After the first ISA master cycle transfers:

PRIO_ISAM < PRIO_IDE0 and PRIO_ISAM < PRIO_IDE1

After IDE channel 0 data transfer and its granting timer expires

PRIO_ISAM > PRIO_IDE0 and PRIO_ISAM < PRIO_IDE1

After IDE channel 1 data transfer and its granting timer not yet expires

PRIO_ISAM > PRIO_IDE0 and PRIO_ISAM < PRIO_IDE1

After IDE channel 1 data transfer and its granting timer expires

PRIO_ISAM > PRIO_IDE0 and PRIO_ISAM > PRIO_IDE1

Note that the priority scheme is used to arbitrate bus usage when ISA master and IDE controller are competing for bus. If there is only one candidate requesting for bus at a time, it can get the bus immediately regardless of it priority.

 

5. USB Host Controller

• Provide USB Host Controller function to meet the Universal Serial Bus Specification version 1.0, with fully compatible to the Open Host Controller Interface Specification for USB Release 1.0
• Provide Legacy Support function based on OpenHCI Legacy Support Interface Specification Release Version 1.01.
• Built-in Root Hub, with two USB Ports integrated.
• Implement circuit and control for the Overcurrent Protection on the USB ports.

The following will be shown the USB System Block Diagram.

1. Integrated Keyboard Controller

The integrated KBC uses hardwired methodology instead of software implementation as the traditional 8042 keyboard BIOS. In this way, keyboard controller can have instant response to all the commands. It also supports Auto A20 gate and Auto Reset Features. Besides, the integrated KBC has a power control feature. After the [Ctrl]+[Alt]+[Backspace] hot keys are pressed, the system will enter the power saving mode. Moreover, the integrated KBC supports the industrial standard PS/2 mouse optionally.

 

Status Register

The status register is an 8 bits read only register located at I/O address hex 64. It has information about the state of the keyboard controller and interface. It may be read at any time.

 

Bit 7 Parity Error

0 : Odd Parity (No Parity Error)

1 : Even Parity (Parity Error)

Bit 6 Time-out Error

0 : No Transmission Time-out Error

1 : Transmission Time-out Error

Bit 5 Auxiliary Output Buffer Full

0 : Keyboard Data

1 : Mouse Data

Bit 4 Inhibit Switch

0 : Keyboard is Inhibited

1 : Keyboard is not Inhibited

Bit 3 Command/Data

0 : Data Byte. Writing to I/O 60h

1 : Command Byte. Writing to I/O 64h

Bit 2 System Flag

This bit may be set to 0 or 1 by writing to system flag bit in the keyboard controller's command byte. It is set to 0 after a power on reset.

Bit 1 Input Buffer Full

0 : Input Buffer Empty

1 : Input Buffer Full. Data has been written into the buffer but the controller has not read the data

Bit 0 Output Buffer Full

0 : Output Buffer Empty

1 : Output Buffer Full. The controller has placed data into its output buffer but the system has not yet read data

 

 

Input/Output Buffer

Input Buffer

The input buffer is an 8 bits write only register located at I/O address hex 60 or 64. Writing to address hex 60 sets a flag, that indicates a data write; writing to address hex 64 sets a flag, indicating a command write. Data written to I/O address hex 60 is sent to the keyboard, unless the keyboard controller is expecting a data byte following a controller command. Data should be written to the controller's input buffer only if the input buffer's full bit in the status register equal 0. The next command are valid keyboard controller commands.

 

Output Buffer

The output buffer is an 8 bits read only register at I/O address hex 60. The keyboard controller uses the output buffer to send scan codes received from the keyboard, and data bytes requested by command to the system. The output buffer should be read only when output buffer's full bit in the status register set to 1.

 

 

 

Commands (I/O Address 64H)

Write I/O Address 64h that is Keyboard BIOS Command:

Command		Keyboard Mode			Keyboard PS/2 Mode
00-1F		Read Internal RAM -- The controller sends value of RAM to output buffer.
20		Read Keyboard Controller's Command Byte -- The controller sends its current Command byte to its output buffer.
21-3F		Read Internal RAM -- The controller sends value of RAM to output buffer.
40-5F		Write Internal RAM -- The next byte of data written to I/O 60h is placed into Internal RAM.
60		Write Keyboard Controller's Command Byte -- The next byte of data written to I/O 60h is placed in the controller's command byte.
	Bit			Bit Definitions
		0 1     2 3 4   5   6     7	1 -- Enable Keyboard Output-Buffer-Full Interrupt. Generates an interrupt when it places keyboard data into its output buffer. In Keyboard Mode: Reserved to 0. In Keyboard PS/2 Mode: 1 -- Enable Mouse-Buffer-Full Interrupt. Generates an interrupt when it places mouse data into its output buffer. 1 -- The controller generates an System Flag. The value written to this bit is placed in the system flat bit of the controller's status register. 1 - Disable Keyboard Lock Switch "KBLOCK". 1 - Disable Keyboard. Disable the Keyboard interface by driving the 'clock' line low. Data is not sent or received. 1 -- Disable Mouse. Disable the mouse interface by driving the 'clock' line low. Data is not sent or received. 1 -- IBM Personal Computer Compatibility Mode. Convert the scan codes received from keyboard to IBM PC. This includes converting a two-byte sequence to the one-byte IBM Personal Computer format. 0 -- Reserved.
61-7F		Write Internal RAM -- The next byte of data written to I/O 60h is placed into Internal RAM.
A0		Read Internal ROM -- The controller sends value to its output buffer that end with a "0".
A1		Read Keyboard Controller's Version - The version code result will be placed to its output buffer.
A4		Reset Internal Register B to 0.			Not Valid
A5		Reset Internal Register B to 0.			Not Valid
A6		Read Internal Register B -- The controller sends value to its output buffer.			Not Valid
A7		Set Internal Register C to 0.			Disable Mouse Device -- This disable the mouse interface by driving the mouse clock line low.
A8		Set Internal Register C to 1.			Enable Mouse Device -- This enable the mouse interface by driving the mouse clock line float.
A9		Read Internal Register C -- The controller sends value to its output buffer.			Mouse Device Interface Test -- Test the controller's mouse clock and data line and place the result to output buffer as follows : 00 -- No error detected. 01 -- The 'Mouse Clock' line is stuck low. 02 -- The 'Mouse Clock' line is stuck high. 03 -- The 'Mouse Data' line is stuck low. 04 -- The 'Mouse Data' line is stuck high.
AA		Self-Test - This commands the controller to perform internal diagnostic tests. A hex 55 is placed in the output buffer if no errors are detected.
AB		Keyboard Interface Test -- This commands the controller to test the keyboard clock and data line. The test result is placed in the output buffer as follows : 00 -- No error detected. 01 -- The 'Keyboard Clock' line is stuck low. 02 -- The 'Keyboard Clock' line is stuck high. 03 -- The 'Keyboard Data' line is stuck low. 04 -- The 'Keyboard Data' line is stuck high.
AD		Disable Keyboard Feature -- This command sets bit 4 of the controller's command byte. This disable the keyboard interface by driving the clock line low. Data will not be sent or received.
AE		Enable Keyboard Interface -- This command clears bit 4 of command byte which release the keyboard interface
B0		Set P10 to 0			Not Valid
B1		Set P11 to 0			Not Valid
B8		Set P10 to 1 (Default)			Not Valid
B9		Set P11 to 1 (Default)			Not Valid
C0		Read Input Port -- This command the controller to read its input port and place the data in its output buffer. This command should be used only if the output buffer is empty.
C1		Set Port P17 to 0 & KBLOCK disable			Set Port P17 to 0 & KBLOCK disable
C2		Not Valid			Place Bit 7-4 of Input Port to status register
C3		Not Valid			Place Bit 3-0 of Input Port to status register
C7		Set Port P17 to 1			Set Prot P17 to 1
CA		Read Internal Register D -- The Internal Register will be placed into its output buffer.
CB		Write Internal Register D -- The next byte of data written to I/O 60h is placed in the controller's Register D.
D0		Read Output Port -- This command causes the controller to read its output port and place data in its output buffer. This command should be issued only if the output buffer is empty.
D1		Write Output Port -- The next byte of data written to I/O 60h is placed in the controller's output port.
D2		Not Valid			Write Keyboard Output Buffer - The next byte of data written to I/O 60h is placed in output buffer as it receive from keyboard.
D3		Not Valid			Write Mouse Output Buffer - The next byte of data written to I/O 60h is placed in output buffer as it receive from mouse.
D4		Not Valid			Write Mouse Device - The next byte of data written to I/O 60h is transmitted mouse device.
D6		Enable P17(KBLOCK) Keyboard Lock Switch (Default)
D7		Disable P17(KBLOCK) Keyboard Lock Switch, P17 define to I/O by C1 & C7 command
F0-FF		Pulse Output Port -- Bits 0 through 3 of controller's output port may be pulsed low for approximately 6us. Bits 0 through 3 of this command indicate which bits are to be pulsed. A 0 indicates that the bit should be pulsed, and a 1 indicate the bit should not be modified.

2. Integrated VGA Controller

Integrated VGA Controller is a high performance 3-in-1 PCI true-color graphics accelerator with video accelerate functions. Integrated VGA Controller video accelerator could work in 3 different modes: standard FC (Feature Connector) mode, direct video interface mode, and PCI multimedia mode.

Furthermore Integrated VGA Controller could work with SW MPEG Player Programs through DCI driver or Direct Draw driver to provide high performance SW MPEG playback to meet future PC trends.

In direct video mode, Integrated VGA Controller could work with the Philips SAA7110 / SAA7111, Sony CXA1790Q, Brooktree Bt815/817/819A (8-bit SPI mode 1, 2), to provide the PC-Video solution and provide the very flexible overlaying ability mentioned above.

In PCI multimedia mode, Integrated VGA Controller supports PCI multimedia design guide Rev. 1.0 spec to meet future potential trend.

The following block diagram will be shown the internal VGA controller.



Figure -32

1. Host Bus Interface

In order to solve the bottleneck of PCI transaction, VGA controller support a dual bus interface, the PCI bus and HOST bus. With HOST bus, VGA controller can directly intercept the memory and I/O transactions sent from CPU. VGA controller can gain more benefit from the HOST bus transaction because the HOST bus support 64 bits and faster clock rate than the 32 bits and lower clock rate of PCI bus. Furthermore, VGA controller would not share the limited bandwidth of PCI bus with other PCI devices. In current structure , the HOST bus support the memory write , memory read , video playback decimation and engine I/O write transaction . The PCI bus transacts the other cycles and transactions from another PCI master.

The HOST bus contains a post write buffer with 8 Qword which can release the HOST bus as soon as possible after it records the address and data into the post write buffer. The data would queue in the post write buffer until the display memory is available, and then write into the display memory.

The VGA controller support the byte merge function which would merge the sequential bytes from different transactions into one stage of post write buffer. The combining of sequential bytes memory writes has a significant performance benefits for the memory bandwidth . We also support the smart write function which would intelligently queue more data in the post write buffer for a while, and then write into display memory one times. It would save a lot of display memory bandwidth of memory write. We can program a register bit to determine how many data would keep in the post write buffer.

The HOST bus support a read ahead cache. When CPU sends the sequential address read commands, it would always hit in the read cache and response the data as soon as possible. It also can reduce the access time from display memory.

 

2. Attribute Controller

The Attribute Controller formats the display for the screen. Display color selection, text blinking, alternate font selection, and underlining are performed by the Attribute Controller.

3. CRT Controller

The CRT Controller generates the HSYNC and VSYNC signals required for the monitor, as well as BLANK# signals required by the Attribute Controller.

4. CRT FIFO

The 64x32 CRT FIFO allows the Display Memory Controller to access the display memory for screen refresh at maximum memory speed rather than at the screen refresh rate. It provides 3 programmable thresholds - CRT/CPU Threshold Low, CRT/CPU Threshold High, and CRT/Engine Threshold High. With adequate programming these three thresholds, the CPU wait-time would be reduced to improve the graphics performance.

5. DDC Controller

The DDC Controller provides two different channels to communicate with the monitor which supports DDC level 1 or DDC level 2B. One is DDC CLK channel which is bi-directional and provides the clock for DDC. The other is DDC DATA channel which is bi-directional and could query some information from monitor.

With the advantage of DDC, VGA BIOS could realize the capability of the connected monitor and take adequate action (such as to program the parameters for higher frame rate, ..., etc.) to make end users feel more comfortable.

6. Display Memory Controller

The Display Memory Controller generates timing for display memory. This includes RAS#, CAS#, and multiplexed-address timing, as well as RAMWE#.

7. DPMS

It provides some registers to control the CRT timing to be compatible with the VESA DPMS specification.

8. Dual-Clock Synthesizer

The Dual-Clock Synthesizer generates MCLK and VCLK with single external reference clock. With this character, we could set the MCLK at the maximum speed which the display memory could work normally, thus it takes the advantage of the real peak memory bandwidth and improves the graphics performance.

9. Graphics Controller

It performs text manipulation, data rotation, color mapping, and miscellaneous operations.

10. Graphics Engine

It is an enhanced 64-bit BitBlt Graphics Engine.

For enhanced 256-color graphics mode, the engine supports the following functions:

* 256 Raster Operation Functions

* Rectangle Fill

* Color/Font Expansion

* Enhanced Color expansion

* Enhanced Font expansion

* Line Drawing

* Built-in 8x8 Pattern Registers

* Built-in 8x8 Mask Registers

* Direct Draw

For 32K or 64K high-color graphics mode, the engine supports the following functions:

* 256 Raster Operation Functions

* Rectangle Fill

* Color/Font Expansion

* Enhanced Color expansion

* Enhanced Font expansion

* Line Drawing

* Built-in 8x8 Mask Registers

* Direct Draw

For 16M-color graphics mode, due to different graphics process methods, the engine supports the following functions:

* Source/Destination BitBlt

* Pattern/Destination BitBlt

* Color/Font Expansion

* Enhanced Font expansion

Descriptions of the graphics engine functions are summarized as follows:

Bit Block Transfer (BitBlt)

BitBlt moves a block of data from one location (source) to another location (destination). It is a ternary operation. The operands could be the source data, the destination data, and the brush pattern. There are three different kinds of BitBlt: from the host memory to the display memory, from the display memory to the host memory, and from one location of the display memory to another location of the display memory.

In the first two cases, the operation simply uses the "move string instruction" (REP MOVS) to move the source data to the destination to accomplish the BitBlt operation. It is called "CPU-driven BitBlt".

In the case of moving from the display memory to the display memory, integrated VGA Controller could gain the advantage of its advanced engine design to solve the problems of memory overlapping during the block transfers. The only effort is to program the adequate parameters.

BitBlt with Mask

When the BitBlt operation deals with the hatched brush pattern, the programmer just needs to set the monochrome mask into Mask Registers and program an adequate BG ROP and Background Color, then the engine would handle the complicated process.

Color/Font Expansion

The color/font expansion is used to expand a monochrome data (one bit per pixel) into a second color format which is n-bit per pixel during a moving operation.

The foreground color and background color is addressed respectively from I/O address 8290h to 8292h and from I/O address 8294h to 8296h. The font patterns are stored in the pattern registers (I/O address 82ACh to 82EBh) or in the off-screen memory which is called Enhanced Color/Font Expansion. These pattern registers store the monochrome bitmap. The BitBlt engine can expand 512 pixels at a time. Thus the font-drawing and monochrome bitmap expansion can be easily accomplished.

Enhanced Color Expansion

If the size of a monochrome bitmap is larger than 512 pixels, there is not enough space in pattern registers to store this bitmap. In this case, the bitmap should be stored in the off-screen display memory instead of the pattern registers. The operation is called Enhanced Color Expansion or Enhanced Font Expansion depended on the data format.

The format written into the off-screen memory of the Enhanced Color Expansion operation is m x n.

When the Command 1 Register D[5] (Enhanced Color Expansion Enable Bit, I/O address 82ABh) is set to 1, the Enhanced Color Expansion mode is enable. The SRC Start Linear Address (I/O address 8280h to 8282h) is used to specify the starting address of the off-screen memory. Integrated Graphics Controller stores the monochrome bitmap into the assigned off-screen memory. Therefore the BitBlt engine could explore more pixels by using the Enhanced Color Expansion.

Enhanced Font Expansion

The Enhanced Font Expansion is very similar to the Enhanced Color Expansion. The major difference is the format stored in the off-screen memory. The format written into the off-screen memory of the Enhanced Font Expansion operation is 8 x n.

When the Command 1 Register D[4] (Enhanced Font Expansion Enable Bit, I/O address 82ABh) is set to 1, the Enhanced Font Expansion mode is enable. The SRC Start Linear Address (I/O address 8280h to 8282h) is used to specify the start address of the off-screen memory. Integrated Graphics Controller stores the monochrome bitmap into off-screen memory byte by byte successively. Therefore the BitBlt engine would expand these pixels by using the Enhanced Font Expansion.

Line Drawing

The Bresenham's Line Algorithm is a well popular algorithm in graphics, which is used to draw a line. The drawing line could be either a solid line or a dashed line. To draw a solid line, we must use one solid foreground color. To draw a dashed line, we'll use two colors specified by the foreground and background color registers. There are several registers involved to control the starting location, pixel count, error term, and line style, etc.

Rectangle Fill

A rectangle area fill is a function to fill a specified rectangle area by using either a solid color (rectangle fill) or a pattern (pattern fill).

Rectangle Fill is simply to fill the destination rectangle with a solid color. The solid color is specified into the foreground color register.

Pattern Fill repeats a source pattern into a destination rectangle. Therefore the pattern registers (I/O address 82ACh to 82EBh) must be specified. The pattern often consists of a background and foreground color because the color expansion would be used in conjunction with the pattern fill.

Raster Operations (Raster Ops or ROPs)

Raster Ops would perform some logical or arithmetic operations on the graphics data. There are 256 raster ops defined by Microsoft. Each raster op code is a Boolean operation with three operands: the source, the selected pattern, and the destination.

Direct Draw

The Windows 95 Game SDK enables the creation of world class computer games. Direct Draw is a component of that SDK that allows direct manipulation of video display memory. In order to enhance the performance of games, Integrated VGA Controller provides some Direct Draw functions.

Since the former engine functions can just support part of Direct Draw capabilities, three new functions are added into the graphics accelerator in order to meet the other Direct Draw functions. They are color key range comparison, alpha blending, and Direct Draw raster operation.

The register format for Direct Draw is different from those of the engine's functions listed above.

To enable Direct Draw, the Direct Draw enable bits must be set to "11". Once Direct Draw is enabled, all of the engine operations are under the "Read-Modify-Write" mode. That is, the destination data have to be read from memory for processing before being written back.

After receiving the destination data, the source and destination data are sent to the color key range comparators to determine whether they are between the high and low color key values. If they are in the color key range, the Direct Draw raster operation (D_Rop) will determine whether the data after alpha blending or the original destination will be written back to memory.

There are two control bits for alpha blending. They are the S_Alpha bit and D_alpha Bit. The table below shows the relationship between these two control bits and the data after alpha blending.

 

 

S_Alpha	D_Alpha	Data after Alpha Blending
0	0	Source
0	1	Destination
1	0	Source
1	1	(Source+Destination)/2

 

11. RAMDAC

The RAMDAC contains the color palette and 24-bit true color DAC.

The color palette contains 256 24-bit entries.

In indirect color modes, it can convert a color code that specifies the color of a pixel into three 6-bit values, one each for red, green, and blue.

In direct color modes, it can convert each three R, G, B values into three 8-bit values when SR6 bit 3 set to 1. Which can perform the Gamma correction function.

In the 24-bit true color DAC is designed for direct color graphics mode. It converts each digital color value to three analog voltages for red, green, and blue.

 

12. Read-ahead Cache

It is a 128-bit cache. With this cache, the times of the operation of display memory read would be reduced, thus increase the performance.

13. Write FIFO

The Write FIFO contains a queue of CPU write accesses to display memory that have not been executed because of memory arbitration. With this queue, the Integrated VGA Controller will release CPU as soon as it records the address and data, and then write into display memory when the display memory is available. Thus CPU performance is increased.

14. Bus Interface

The Integrated VGA Controller dedicatedly supports 32-bit PCI Local Bus Standard Revision 2.1. Furthermore Integrated VGA Controller supports PCI burst write to take advantage of PCI bus advanced feature to further improve performance. But PCI burst read is not supported since it has very little impact on performance in graphics application.

15. DRAM Support

Integrated VGA Controller supports 0.5 MB, 1 MB, 1.5 MB, 2 MB, 2.5 MB, 3 MB, 3.5 MB, and 4 MB FPM/EDO DRAM and Synchronous DRAM configuration. SiS chp will assert the RAS0#/CS#, MA0A, MA1A, SCAS0# and SRAS0# (memory Bank0) when the integrated VGA controller access the main memory.

16. Video Memory Data Bus Architecture

The Integrated VGA Controller uses the 64-bit DRAM data bus with peak video memory bandwidth of 220 MByte/sec for FPM DRAM with 55Mhz MCLK.

In 2MByte DRAM configuration, Integrated VGA Controller can support 1024x768x32K color, 1024x768x64K color, and 800x600x16M color resolutions with no degradation in the graphics performance.

In 4MByte DRAM configuration, Integrated VGA Controller can support 1024x768x16M color, 1280x1024x32K color, and 1280x1024x64K color resolutions. These resolutions are not easily implemented by the regular Graphics Controller architecture.

17. Internal Dual-Clock Synthesizer

Integrated VGA Controller has built-in a dual-clock synthesizer to generate the MCLK and VCLK. This clock synthesizer could generate several variable frequencies, thus it could provide the flexibility for selecting the working frequency.

The following block diagram is for clock synthesizer:



where PD is phase detection,

CP is charge pump,

VCO is voltage controlled oscillator,

fr is reference frequency, and

fd is desired frequency.

 

The operation of clock synthesizer is described as follow:

When the synthesizer outputs the steady frequency, it means that

fr/DeNumerator = fd*Post Scaler /(Divider*Numerator).

i.e.

fd=fr*(Numerator/DeNumerator)*(Divider/Post Scaler).

With this formula, we could select adequate values for Numerator, DeNumerator, Divider, and Post Scaler to obtain the desired frequency.

The planned Video Clocks (VCLK) are as follow: (units: MHz)

25.175	28.322	40.000	50.000	77.000
36.000	44.889	135.000	120.000	80.000
31.500	110.000	65.000	75.000	94.500

These frequencies are compatible with ICS2494-275 or -280.

Other video clocks would be added to the scheme after verified OK.

The planned Memory Clocks (MCLK) are from 50 MHz to 80 MHz with resolution 2 MHz.

Higher memory clocks would be added after verified OK.

 

18. Power Management

To satisfy the power saving for Green PC, Integrated VGA Controller supports the control protocol of DPMS (Display Power Management Signaling) proposed by VESA Monitor Committee. This protocol can reduce the VGA Monitors' power consumption.

Integrated VGA Controller has built-in two timers for stand-by and suspend modes that can be programmed from 2 minutes to 30 minutes (2 min./increase) with the extended registers.

Integrated VGA Controller also supports forcing the video subsystem into stand-by, suspend, or off modes with the extended registers.

Power saving is done by blocking HSYNC and/or VSYNC signals to the VGA monitor. The sources of wake-up are from the monitoring of keyboard, hardware cursor, and/or video memory read/write. The overview of the signal blocking requirements are as follows:

POWER MANAGEMENT STATE	HORIZONTAL SYNC	VERTICAL SYNC	VIDEO DISPLAY
ON	Pulses	Pulses	Yes
Stand-By	No Pulses	Pulses	No
Suspend	Pulses	No Pulses	No
OFF	No Pulses	No Pulses	No

19. Advanced Configuration and Power Interface Specification (ACPI)

In order to achieve power saving for Green PC , VGA controller support ACPI specification . When the OS determines that the graphics display is no longer needed , it will assert the GR_SUS# signal to place the graphics subsystem in the D3 power off state . In this low power state , the VGA controller will firstly check whether the PCI_bus state machine , the HOST_bus state machine , the DRAM state machine and the ENGINE state machine are on the idle state . If these conditions meet , the VGA controller will deassert HSYNC , VSYNC and let Line-buffer, SRAM and DAC sequencely enter the low power state and then gate off the internal clocks like memory clock and video clock . In addition to gate off above internal clocks , we also gate off the rapidly changed signals like PCI data and HOST data and deassert the PCI device select signal and the HOST device select signal , i.e , the VGA controller will completely isolated form the PCI_bus and HOST_bus . Finally , The OS will deassert the GR_CLKPWR# signal to remove power from the graphics clock generator .

When a wake-up event occurred , VGA controller must enter to Power-On state in sequence. It will firstly assert the GR_CLKPWR# signal to supply power to the graphics clock generator and then turn on internal clocks . When the VGA controller delay some fixed time to stabilize the power supply , it will deassert the GR_SUS# signal to turn on Line-buffer , SRAM , DAC , HSYNC and VSYNC.

Note that the GR_SUS# and GR_CLKPWR# are the internal signals.

20. Resolutions Supported

Resolution	0.5 MB	1 MB	1.5 MB	2 MB	2.5 MB	3MB	3.5 MB	4 MB
640x480x8	*	*	*	*	*	*	*	*
640x480x16		*	*	*	*	*	*	*
640x480x24		*	*	*	*	*	*	*
800x600x4	*	*	*	*	*	*	*	*
800x600x8	*	*	*	*	*	*	*	*
800x600x16		*	*	*	*	*	*	*
800x600x24			*	*	*	*	*	*
1024x768x4	*	*	*	*	*	*	*	*
1024x768x8		*	*	*	*	*	*	*
1024x768x16			*	*	*	*	*	*
1024x768x24					*	*	*	*
1280x1024x4		*	*	*	*	*	*	*
1280x1024x8			*	*	*	*	*	*
1280x1024x16						*	*	*

Except these real resolution modes, Integrated VGA Controller is also built-in virtual screen mode which could support up to 2048x2048 resolution.

21. Turbo Queue

In Integrated VGA Controller, the graphics engine performs the acceleration functions via the acceleration commands stored in the command queue. The command queue is a FIFO (First In First Out) and ring structure. i.e. If an acceleration command is filled in the last stage of the command queue, then the following acceleration command would be filled in the first stage of the command queue.

Once this command queue is congested, the CPU's request will be pending until the command queue has free space to accept more acceleration commands. This would downgrade the graphics system performance severely. Thus the length of command queue will dominate the performance of the graphics engine.

To lengthen the command queue as long as required, Integrated VGA Controller provides two different kinds of command queue. The first one is built in Integrated VGA Controller, which is called Hardware Command Queue. The other one is built in the off-screen display memory, which is called Turbo Queue.

The Hardware Command Queue is a 32 doublewords queue built in front of the graphics engine. Since the average length of an engine command is 8 doublewords, it could be regarded as 5 stages command queue, the first one is in the active state and the last four are in the wait states.

The Turbo Queue is an extraordinary structure developed and patent pending by SiS Corp.

The system configuration of the two command queues and the graphics engine is shown in the following diagram.



Figure -33 Turbo Queue Architecture

The Turbo Queue is also a FIFO and ring structure as stated before. The size of the Turbo Queue in Integrated VGA Controller is 32K bytes. Thus the stages of graphics engine could be regarded as infinity. It could get rid of the disadvantages of the CPU waiting problems due to the limited length of command queue and It could get extra high graphics performance.

To program the extended register SR2C (Turbo Queue Base Address Register) could allocate the Turbo Queue into the off-screen region of the display memory automatically. Once the commands in the Hardware Command Queue were moved into the Turbo Queue, the free space in the Hardware Command Queue could be vacated to store the next acceleration command and the condition of CPU waiting could be avoided. If both the command queues are not empty, the graphics engine would perform the commands in Turbo Queue first until Turbo Queue is empty.

22. Video Accelerator

Video Password/Identification Register

A video registers protection is implemented in the index 80h of CRT index register 3D4. To disable the protection, the software must first match the protection key value of 86h. If not match, read/write to any of the video associated registers are denied.

Video Capture and PlayBack

Integrated VGA Controller video accelerator can work in three different modes: standard FC (feature connector) mode, direct video mode, and PCI multimedia mode.

In standard FC mode, Integrated VGA Controller supports standard FC operation.

In direct video mode, Integrated VGA Controller could work with the Philips SAA7110 / SAA7111, Sony CXA1790Q, and Brooktree Bt815/817/819A (8-bit SPI mode 1, 2) to provide the PC-Video solution and provide the very flexible overlaying ability mentioned above.

In PCI multimedia mode, Integrated VGA Controller supports PCI multimedia design specification to meet future potential trend.

Integrated VGA Controller also supports the industry standard FC spec to provide a standard video link to the third-parties' video adapters.

Furthermore in PCI multimedia mode, Integrated VGA Controller supports PCI multimedia design guide Rev. 1.0 spec to meet future potential trend.

Feature Connector Interface

In standard feature connector mode, Integrated VGA Controller would transfer the graphics data to the connected video adapter for overlay and can accept the video data from the connected video adapter.

The data input/output direction of Integrated VGA Controller is controlled by the ESYNC, EVDCLK, EVIDEO pins and is automatically controlled by BIOS.

Video Capture Window



Integrated VGA Controller provides video capture windowing to select a part of input video to be captured into video frame buffer. This capture window is defined by four parameter: video data horizontal start (VDHES), video data horizontal end (VDHEE), video data vertical start (VDVES), and video data vertical end (VDVEE).

There are the video data horizontal counter and the video data vertical counter inside Integrated VGA Controller. The video data horizontal counter is reset at the positive edge of signal BLANK# and counted up by PCLK. The video data vertical counter is reset at the positive edge of ESYNC and counted up by positive of BLANK#. When the value of the video data horizontal counter is equal to or greater than VDHES and the video data vertical counter is equal to or greater than VDVES, the video data capture starts or continues. After the value of the video data horizontal counter is equal to or greater than VDHEE or the video data vertical counter is equal to or greater than VDVEE, the video capture ends.

Video Captured Down Scaling

Integrated VGA Controller provides independent X-Y down scaling of the captured video image in integer increments of 1/64. Images may be scaled down to n/64 (n = 1 ~ 64) of the original image size to support video icons for graphics user interfaces, or to reduce the memory bandwidth. The scaling factor is controlled by HDSF and VDSF, which ranging from 0 to 63, and the scaling factors are (64-HDSF)/64 in horizontal and (64-VHSF)/64 in vertical.

Video Capture FIFO

The scaled-down video data would be fed into the video capture FIFO before being stored to display memory. The 64x16 video capture FIFOs serve as buffers between the video capture mechanisms and the display memory, are provided to fit the bandwidth limitation of the display memory during video image capture operation.

Multi-format Video Frame Buffer

The video frame buffer of Integrated VGA Controller is shared with graphics frame buffer and is a multi-format frame buffer. It could accept 16-bpp YUV422, RGB555, and RGB565 and 12-bpp YUV420(plane mode) color format.

The decompression CODEC, hardware or software, could fill the valid decompressed video frame data into the off-screen video frame buffer through the PCI local bus.

The other PCI motion video card or CPU can transfer the video data through PCI local bus directly into video frame buffer.

Thus Integrated VGA Controller can overlay the video on the screen.

YUV420 plane mode

Integrated controller supports YUV420 plane mode. The data rate of YUV420 is 12-bpp which is smaller than 16-bpp of YUV422. So that the data bandwidth can be reduced and improve the video playback performance. The YUV420 mode need three start address for Y, U and V plane, and two offset for Y and U,V plane.

Video Playback Line Buffers

When CRT refresh the screen, the video data must be overlaid with graphics data. Therefore the video data would first be read out from off-screen video frame buffer into the video playback line buffers for further handling.

The video playback line buffers serve as buffers between display memory and the playback mechanisms, are provided to fit the limitation of the display memory during video playback operation.

When video playback function is disabled, the line buffers can be used as CRT FIFO to increase the CRT FIFO size to 2k bytes.

Color Space Conversion & Color Format Conversion

If the data read from the video frame buffer is in YUV422, the real time YUV-to-RGB converter will be turn on. The video data would be converted to RGB888 format for successive processing. The YUV422 are converted following the CCIR601-2 standard.

If the data read from the video frame buffer is in RGB format, the YUV-to-RGB converter would be bypassed. All the RGB565 and RGB555 format are supported and then would be converted to RGB888 format.

Horizontal Interpolation DDA

The DDA (Digital Differential Accumulator) using the following mathematical calculation with 2-tap, N-phase and scaling up factor UFACT (from J points scaling up to J * UFACT points):

Destination[i] = (1 - Weight) * Source[j] + Weight * Source[j+1]

j = TRUNC(i / UFACT)

Weight" = TRUNC(i / UFACT) - j

However since the Weight" is not an integer, the multiplication is hard to implement and therefore the following Weight is used for calculation.

Weight = TRUNC(Weight" * N) / N

The Integrated VGA Controller built-in an X-interpolation DDA mechanism to get better video stretching quality. The interpolation accuracy of DDA mechanism is 2-tap and 8-phase.

Vertical Interpolation DDA

The Integrated VGA Controller built-in a Y-interpolation DDA mechanism and two line buffers mechanism to get better video stretching quality. The interpolation accuracy of DDA mechanism is 2-tap and 8-phase.

Video Playback Horizontal Zooming

The playback video data can be horizontal zoom-in in 64/n factor (n = 1 ~ 64) and zoom-out in about m/16 factor (m = 1 ~ 16). The zooming factor (HPFACT) is controlled by 4-bit integer part and 6-bit fraction part. The horizontal video size will be zoomed to 1/HPFACT. If HPFACT<1, it will performing horizontal up scaling. If HPFACT>1, it will performing horizontal down scaling.

Video Playback Vertical Zooming

The playback video data can be vertical zoom-in in 64/n factor (n = 1 ~ 64) and zoom-out in arbitrary factor. The zooming factor (VPFACT) is controlled by 6-bit fraction part. The video size will be zoomed to 1/VPFACT. Since the VPFACT is always less than 1, therefore you can only perform vertical up scaling by this factor. The vertical down scaling can be done by multiplying the Video Frame Buffer Offset with an integer I. Then the vertical video size will be zoomed to 1/(I*VPFACT).

Video Data Blending

The pixels of graphics data can be blended by graphics data alpha value, then add with the blended video data to generate blended data. The accuracy of the blending is 4 bits, the 4 MSBs of Graphic data alpha value register.

The pixels of video data can be blended by video data alpha value, then add with the blended graphics data to generate blended data. The accuracy of the blending is 4 bits, the 4 MSBs of Video data alpha value register.

 

Color Keying

A control signal is generated by comparing the 24 bits graphics data to the 24 bits color key low value and 24 bits color key high value. The bit number is dependent on color depth used. If the graphics data value is between the two color key values ( all of three RGB parts), the color key is detected. This comparison mechanism can be disable by setting the video window size to zero, i.e. X-start=0, X-end=0, Y-start=0, and Y-end=0.

Chroma Keying

A control signal is generated by comparing the 24 bits video data to the 24 bits chroma key low value and 24-bit chroma key high value. The chroma key can be YUV or RGB format. If the video data value is between two chroma key values ( all of three RGB or YUV parts), the chroma key is detected.

Graphics & Video Overlay

The overlay of the graphics data and the video data is performed by color keying and chroma keying method. The overlay operation is set by Key Overlay Operation Mode Register. The operation is defined below:

Operation Mode	Operation
0000	always select graphics data
0001	select blended data when color key and chroma key, otherwise select graphics data
0010	select blended data when color key and not chroma key, otherwise select graphics data
0011	select blended data when color key, otherwise select graphics data
0100	select blended data when not color key and chroma key, otherwise select graphics data
0101	select blended data when chroma key, otherwise select graphics data
0110	select blended data when color key xor chroma key, otherwise select graphics data
0111	select blended data when color key or chroma key, otherwise select graphics data
1000	select blended data when not color key and not chroma key, otherwise select graphics data
1001	select blended data when color key xnor chroma key, otherwise select graphics data
1010	select blended data when not chroma key, otherwise select graphics data
1011	select blended data when color key or not chroma key, otherwise select graphics data
1100	select blended data when not chroma key, otherwise select graphics data
1101	select blended data when not color key or chroma key, otherwise select graphics data
1110	select blended data when not color key or not chroma key, otherwise select graphics data
1111	always select blended data

Video Window Control Registers

The video window area is defined by six registers that specify a rectangular region by X-start, X-end, Y-start, and Y-end (X: Horizontal, Y: Vertical).

The location of the video window is referenced to the VGA sync signals.

The size of the video window is defined in VGA pixels and lines.

Video Panning

The displayed video image could be panned around the captured video image by setting the video display starting address. i.e. You may selectively display any part of the captured video image. The video display starting address is equal to the video frame buffer starting address adds the panning offset.

Overlay Memory Data

The display memory is configured to two areas: one is the graphics area (which is the actual screen display area) storing graphics pixel data, and the other is the video area (which is also called off-screen area) storing the video pixel data.

In the graphics area, the corresponding video window area is reserved with the color key value. During the CRT scan period, a comparison of graphics data with color key data is performed. Once a match meet, the CRT output path would be switched from graphics path to video path to display the video data.

When the shared-memory architecture is used, the video frame buffer could be anywhere of the system memory, independent with the location of the graphics frame buffer. This provides more flexibility for video control application program. The video frame buffer should be set to Non-Cacheable and non-swapable.

23. Video Playback Contrast Enhancement and Brightness Control

To achieve higher video quality, the Integrated VGA Controller built-in the Contrast Enhancement and Brightness Control mechanism.

For Contrast Enhancement, first, the brightness mean value is calculated by some pixels and some frames. The number of sampled pixels and frames is programmable by registers. Contrast Enhancement mechanism then increases the difference between the video data and mean value. The increasing rate is programmed by gain. The value of gain is from 1.0 to 1.4375.

The Brightness of video data can also be controlled. The Brightness is a 2's complement value from -128 to +127. This value is then added with the video data to increase or decrease the brightness of video.

 

24. Video CPU Write Data Decimation

The DRAM bandwidth is not enough under some high resolution and high color depth graphics modes, so the video overlay cannot perform under these modes. The Video CPU Write Data Decimation mechanism can decimate two continuous pixels of video to one pixel to reduce the video bandwidth. The video performance can be improved but video quality will be downgraded slightly.

 

25. Signature Analysis

The signature analysis is provided to automatically test the graphics data which is the input of the DAC. This technique is based on the concept of cyclic redundancy checking (CRC) and is realized in hardware using linear feedback shift registers (LFSRs). It is composed of a 24-bit signature generator register which is called multiple-input signature register (MISR, shown in the following figure) and is used to ensure a unique signature of different patterns.

For a given test image, the signature analysis could get a right unique signature number. If an error occurs in the controller or the data manipulation, it would result in a different wrong signature number as compared to the pre-calculated signature value. Thus a test technician could sort the good or bad chips more quickly and accurately and requires no visual inspection of the screen for errors in the mass product environment. This could save significant testing time. If the display screen includes blinking attributes or a blinking cursor, then the signature will be different when blink-off and blink-on for those frames. Assume all error patterns are equally likely, then the probability of failing to detect an error by the MISR is approximately 0.0000000596.

To match the inputs of MISR, the 24-bit graphics data (i.e. the input of the DAC of the RAMDAC) would be first converted into 16-bit data. The corresponding transfer function of the MISR of the following figure is

p(x) = 1 + a1x + a2x2 + a3x3 + ... + an xn

where can be either 0 or 1. Integrated VGA Controller sets the parameters of the signature register as

p(x) = 1 + x20 + x21 + x23 + x24

Once the software enables the signature analysis function, Integrated VGA Controller could test itself intelligently and automatically. This function could also be disabled by the extended control register for power saving purposes.



Figure -34 Multi-Input Signature Register (MISR)

26. Compatibility

The Integrated VGA Controller is fully compatible with all standard IBM VGA modes and EGA, CGA, MDA, and Hercules modes.

27. Software Support

To fully utilize and support the Integrated VGA Controller hardware features, SiS has developed a high-performance VESA extension compliant BIOS.

Extended graphics and text modes are supported by software application drivers developed by SiS. The following applications are currently supported:

* 3D Studio Ver. 3.0 & 4.0

* AutoCAD/386 Release 11, 12, 13

* Auto Shade/386 Ver. 2.0

* GEM 3.0/Ventura 2.0

* Lotus 1-2-3/Symphony Ver. 3.x

* MicroSoft Windows 3.1

* MicroSoft Windows 95

* MicroSoft Windows NT Ver. 3.1 & 3.5

* OrCad (SDT/VST/PCB) Rel 4

* OS/2 Presentation Manager 2.1 & 3.0

* P-CAD Ver. 6.06

* VersaCAD/386 Ver. 2.1

* Word Perfect 5.x & 6.0

Video operation are supported by software application drivers developed by SiS. The following applications are currently supported:

* Microsoft Video For Windows

* DCI driver

* Direct Draw driver

28. Mode Table

Standard VGA Modes

MODE	TYPE	DISPLAY SIZE	COLORS SHADES	ALPHA FORMAT	BUFFER START	BOX SIZE	MAX. PAGES
0	A/N	320x200	16	40x25	B800	8x8	8
0*	A/N	320x350	16	40x25	B800	8x14	8
0+	A/N	360x400	16	40x25	B800	9x16	8
1	A/N	320x200	16	40x25	B800	8x8	8
1*	A/N	320x350	16	40x25	B800	8x14	8
1+	A/N	360x400	16	40x25	B800	9x16	8
2	A/N	640x200	16	80x25	B800	8x8	8
2*	A/N	640x350	16	80x25	B800	8x14	8
2+	A/N	720x400	16	80x25	B800	9x16	8
3	A/N	640x200	16	80x25	B800	8x8	8
3*	A/N	640x350	16	80x25	B800	8x14	8
3+	A/N	720x400	16	80x25	B800	9x16	8
4	APA	320x200	4	40x25	B800	8x8	1
5	APA	320x200	4	40x25	B800	8x8	1
6	APA	640x200	2	80x25	B800	8x8	1
7	A/N	720x350	4	80x25	B000	9x14	8
7+	A/N	720x400	4	80x25	B000	9x16	8
0D	APA	320x200	16	40x25	A000	8x8	8
0E	APA	640x200	16	80x25	A000	8x8	4
0F	APA	640x350	2	80x25	B000	8x14	2
10	APA	640x350	16	80x25	A000	8x14	2
11	APA	640x480	2	80x30	A000	8x16	1
12	APA	640x480	16	80x30	A000	8x16	1
13	APA	320x200	256	40x25	A000	8x8	1

NOTE: 1. A/N: Alpha/Numeric

2. APA: All Point Addressable (Graphics)

MODE	DISPLAY SIZE	COLORS SHADES	FRAME RATE.	H-SYNC.	VIDEO FREQ.
0	320x200	16	70	31.5 K	25.1 M
0*	320x350	16	70	31.5 K	25.1 M
0+	360x400	16	70	31.5 K	28.3 M
1	320x200	16	70	31.5 K	25.1 M
1*	320x350	16	70	31.5 K	25.1 M
1+	360x400	16	70	31.5 K	28.3 M
2	640x200	16	70	31.5 K	25.1 M
2*	640x350	16	70	31.5 K	25.1 M
2+	720x400	16	70	31.5 K	28.3 M
3	640x200	16	70	31.5 K	25.1 M
3*	640x350	16	70	31.5 K	25.1 M
3+	720x400	16	70	31.5 K	28.3 M
4	320x200	4	70	31.5 K	25.1 M
5	320x200	4	70	31.5 K	25.1 M
6	640x200	2	70	31.5 K	25.1 M
7*	720x350	4	70	31.5 K	28.3 M
7+	720x400	4	70	31.5 K	28.3 M
0D	320x200	16	70	31.5 K	25.1 M
0E	640x200	16	70	31.5 K	25.1 M
0F	640x350	2	70	31.5 K	25.1 M
10	640x350	16	70	31.5 K	25.1 M
11	640x480	2	60	31.5 K	25.1 M
12	640x480	16	60	31.5 K	25.1 M
13	320x200	256	70	31.5 K	25.1 M

NOTE: i - interlaced mode

n - noninterlaced mode

Enhanced Video Modes

MODE	TYPE	DISPLAY SIZE	COLORS SHADES	ALPHA FORMAT	BUFFER START	BOX SIZE	MAX. PAGES
22	A/N	1056x352	16	132x44	B800	8x8	2
23	A/N	1056x350	16	132x25	B800	8x14	4
24	A/N	1056x364	16	132x28	B800	8x13	4
25	APA	640x480	16	80x60	A000	8x8	1
26	A/N	720x480	16	80x60	B800	9x8	3
29	APA	800x600	16	100x37	A000	8x16	1
2A	A/N	800x600	16	100x40	B800	8x15	4
2D	APA	640x350	256	80x25	A000	8x14	1
2E	APA	640x480	256	80x30	A000	8x16	1
2F	APA	640x400	256	80x25	A000	8x16	1
30	APA	800x600	256	100x37	A000	8x16	1
37	APA	1024x768	16	128x48	A000	8x16	1
38	APA	1024x768	256	128x48	A000	8x16	1
39	APA	1280x1024	16	160x64	A000	8x16	1
3A	APA	1280x1024	256	160x64	A000	8x16	1
40	APA	320x200	32K	40x25	A000	8x8	1
41	APA	320x200	64K	40x25	A000	8x8	1
42	APA	320x200	16.8M	40x25	A000	8x8	1
43	APA	640x480	32K	80x30	A000	8x16	1
44	APA	640x480	64K	80x30	A000	8x16	1
45	APA	640x480	16.8M	80x30	A000	8x16	1
46	APA	800x600	32K	100x37	A000	8x16	1
47	APA	800x600	64K	100x37	A000	8x16	1
48	APA	800x600	16.8M	100x37	A000	8x16	1
49	APA	1024x768	32K	128x48	A000	8x16	1
4A	APA	1024x768	64K	128x48	A000	8x16	1
4B	APA	1024x768	16.8M	128x48	A000	8x16	1
4C	APA	1280x1024	32K	160x64	A000	8x16	1
4D	APA	1280x1024	64K	160x64	A000	8x16	1

NOTE: 1. A/N: Alpha/Numeric

2. APA: All Point Addressable (Graphics)

MODE	DISPLAY SIZE	COLORS SHADES	FRAME RATE.	H-SYNC.	VIDEO FREQ.
22	1056x352	16	70	30.5 K	40.0 M
23	1056x350	16	70	30.5 K	40.0 M
24	1056x364	16	70	30.5 K	40.0 M
25	640x480	16	60	31.5 K	25.1 M
26	720x480	16	60	31.5 K	25.1 M
29	800x600	16	56	35.1 K	30.0 M
29*	800x600	16	60	37.9 K	40.0 M
29+	800x600	16	72	48.0 K	50.0 M
29#	800x600	16	75	46.8 K	50.0 M
29##	800x600	16	85	53.7 K	56.3 M
2A	800x600	16	56	35.1 K	36.0 M
2D	640x350	256	70	31.5 K	25.1 M
2E	640x480	256	60	31.5 K	25.1 M
2E*	640x480	256	72	37.9 K	31.5 M
2E+	640x480	256	75	37.5 K	31.5 M
2E++	640x480	256	85	43.4 K	36.0 M
2F	640x400	256	70	31.5 K	25.1 M
30	800x600	256	56	35.1 K	36.0 M
30*	800x600	256	60	37.9 K	40.0 M
30+	800x600	256	72	48.0 K	50.0 M
30#	800x600	256	75	46.8 K	50.0 M
30##	800x600	256	85	53.7 K	56.3 M
37i	1024x768	16	87	35.5 K	44.9 M
37n	1024x768	16	60	48.4 K	65.0 M
37n+	1024x768	16	70	56.5 K	75.0 M
37n#	1024x768	16	75	60.2 K	80.0 M
37n##	1024x768	16	85	68.7 K	94.5 M
38i	1024x768	256	87	35.5 K	44.9 M
38n	1024x768	256	60	48.4 K	65.0 M
38n+	1024x768	256	70	56.5 K	75.0 M
38n#	1024x768	256	75	60.2 K	80.0 M
38n##	1024x768	256	85	68.7 K	94.5 M
39i	1280x1024	16	87	48.8 K	80.0 M
39n	1280x1024	16	60	65.0 K	110.0 M
39n+	1280x1024	16	75	80.0 K	135.0 M
3Ai	1280x1024	256	87	48.8 K	80.0 M
3An	1280x1024	256	60	65.0 K	110.0 M
3An+	1280x1024	256	75	80.0 K	135.0 M
40	320x200	32K	70	31.5 K	25.1 M
41	320x200	64K	70	31.5 K	25.1 M
42	320x200	16.8M	70	31.5 K	25.1 M
43	640x480	32K	60	31.5 K	25.1 M
43*	640x480	32K	72	37.9 K	31.5 M
43+	640x480	32K	75	37.5 K	31.5 M
43++	640x480	32K	85	43.4 K	36.0 M
44	640x480	64K	60	31.5 K	25.1 M
44*	640x480	64K	72	37.9 K	31.5 M
44+	640x480	64K	75	37.5 K	31.5 M
44++	640x480	64K	85	43.4 K	36.0 M
45	640x480	16.8M	60	31.5 K	25.1 M
45*	640x480	16.8M	72	37.9 K	31.5 M
45+	640x480	16.8M	75	37.5 K	31.5 M
45++	640x480	16.8M	85	43.4 K	36.0 M
46	800x600	32K	56	35.1 K	36.0 M
46*	800x600	32K	60	37.9 K	40.0 M
46+	800x600	32K	72	48.0 K	50.0 M
46#	800x600	32K	75	46.8 K	50.0 M
46##	800x600	32K	85	53.7 K	56.3 M
47	800x600	64K	56	35.1 K	36.0 M
47*	800x600	64K	60	37.9 K	40.0 M
47+	800x600	64K	72	48.0 K	50.0 M
47#	800x600	64K	75	46.8 K	50.0 M
47##	800x600	64K	85	53.7 K	56.3 M
48	800x600	16.8M	56	35.1 K	36.0 M
48*	800x600	16.8M	60	37.9 K	40.0 M
48+	800x600	16.8M	72	48.0 K	50.0 M
48#	800x600	16.8M	75	46.8 K	50.0 M
48##	800x600	16.8M	85	53.7 K	56.3 M
49i	1024x768	32K	87	35.5 K	44.9 M
49n	1024x768	32K	60	48.4 K	65.0 M
49n+	1024x768	32K	70	56.5 K	75.0 M
49n#	1024x768	32K	75	60.2 K	80.0 M
49n##	1024x768	32K	85	68.7 K	94.5 M
4Ai	1024x768	64K	87	35.5 K	44.9 M
4An	1024x768	64K	60	48.4 K	65.0 M
4An+	1024x768	64K	70	56.5 K	75.0 M
4An#	1024x768	64K	75	60.2 K	80.0 M
4An##	1024x768	64K	85	68.7 K	94.5 M
4Bi	1024x768	16.8M	87	35.5 K	44.9 M
4Bn	1024x768	16.8M	60	48.4 K	65.0 M
4Bn+	1024x768	16.8M	70	56.5 K	75.0 M
4Bn#	1024x768	16.8M	75	60.2 K	80.0 M
4Bn##	1024x768	16.8M	85	68.7 K	94.5 M
4Ci	1280x1024	32K	89	48.8 K	80.0 M
4Di	1280x1024	64K	89	48.8 K	80.0 M

NOTE: i - interlaced mode

n - noninterlaced mode

* For the limitation of memory bandwidth in 1MB DRAM configuration, the following video modes is not supported in 1MB configuration: modes 45*, 45+, 46+, 46#, 47+, and 47#.

 

3. Multiplexed pins

Several SiS Chip I/O pins have multiple functions, the following table will provide the condition to define the pin for each function.

SiS5582 Ball No.	SiS5581 Ball No.	Pin Name	Description
N29	U29	MA0B	Set Register 57 bit 1 to "0" in Host to PCI Bridge Configuration Register
		SRAS1#	Set Register 57 bit 1 to "1" in Host to PCI Bridge Configuration Register
N25	U25	MA1B	Set Register 57 bit 1 to "0" in Host to PCI Bridge Configuration Register
		SCAS1#	Set Register 57 bit 1 to "1" in Host to PCI Bridge Configuration Register
J27	AA27	GPO3	Set ACPI/SCI Offset Register 1Ch bit 4 to "1" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		MA12	Set ACPI/SCI Offset Register 1Ch bit 4 to "0" in PCI to ISA Bridge Configuration Register
J28	AA28	GPO4	Set ACPI/SCI Offset Register 1Ch bit 5 to "1" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		MA13	Set ACPI/SCI Offset Register 1Ch bit 5 to "0" in PCI to ISA Bridge Configuration Register
J29	AA29	GPO6	Set ACPI/SCI Offset Register 1Ch bit 6 to "0" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		MA14	Set ACPI/SCI Offset Register 1C bit 6 to "1" in PCI to ISA Bridge Configuration Register
D26	AF26	GPIO7	Set Register 6Ah bit 4 to "0" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		OCO#	Set Register 6A bit 4 to "1" and 6A bit 6 to "1" in PCI to ISA Bridge Configuration Register
		OCI2#	Set Register 6A bit 4 to "1" and 6A bit 6 to "0" in PCI to ISA Bridge Configuration Register
H26	AB26	GPIO8	Set Register 6Ah bit 5 to "0" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		OCI1#	Set Register 6A bit 5 to "1" in PCI to ISA Bridge Configuration Register
D27	AF27	IOCHK#	Set ACPI/SCI Offset Register 24 bit 6 to "0" in PCI to ISA Bridge Configuration Register
		GPIO9	Set Register 40h bit7 to "1" and ACPI/SCI Offset Register 24h bit 6 to "1" in PCI to ISA Bridge Configuration Register and Set ACPI/SCI Offset Register 1C bit 9 to "1" in PCI to ISA Bridge Configuration Register.
		THRM#	Set ACPI/SCI Offset Register 24 bit 6 to "1" in PCI to ISA Bridge Configuration Register and Set ACPI/SCI Offset Register 1C bit 9 to "0" in PCI to ISA Bridge Configuration Register
B7	AH7	GPIO10	Set Auto Power Control Register II bit 1 to "0" in APC Control Registers and set Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register
		ACPILED	Set Auto Power Control Register II bit 1 to "1" in APC Control Registers
D6	AF6	OSCO	Connect PSRSTB# to Battery circuit
		RTCCS#	Pull-low resistor on PSRSTB# signal
E6	AE6	OSCI	Connect PSRSTB# to Battery circuit
		IRQ8#	Pull-low resistor on PSRSTB# signal
C8	AG8	RTCALE#	Connect PSRSTB# to Battery circuit
		ONCTL#	Pull-low resistor on PSRSTB# signal
B19	AH19	KBCLK	Set Register 70 bit 3 to "1" in PCI to ISA Bridge Configuration Register.
		GPIO2	Set Register 70 bit 3 to "1" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register, and set Register 1Dh bit 2 to ‘1’ in ACPI/SCI Offset Register.
A19	AJ19	KBDAT	Set Register 70h bit 3 to "1" in PCI to ISA Bridge Configuration Register.
		IRQ1	Set Register 70h bit 3 to "0" in PCI to ISA Bridge Configuration Register.
D19	AF19	PMCLK	Set Register 70h bit 3 to "1" and 70h bit 4 to "1" in PCI to ISA Bridge Configuration Register.
		GPIO1	Set Register 70 bit 3 to "0" and Register 40h bit7 to "1" in PCI to ISA Bridge Configuration Register, and set Register 1Dh bit 1 to ‘1’ in ACPI/SCI Offset Register.
B20	AH20	PMDAT	Set Register 70h bit 3 to "1" and 70h bit 4 to "1" in PCI to ISA Bridge Configuration Register.
		IRQ12	Set Register 70h bit 3 to "1" in PCI to ISA Bridge Configuration Register.
C20	AG20	KLOCK#	Set Register 70 bit 4 to "1" in PCI to ISA and 57 bit 0 to "1" in Host to PCI Configuration Register
		GPIO0	Set Register 70 bit 4 to "0" and 40h bit7 to "1" in PCI to ISA and 57 bit 0 to "1" in Host to PCI Bridge Configuration Register, and set Register 1Dh bit 0 to ‘1’ in ACPI/SCI Offset Register.
		RAMWC#	Set Register 57h bit 0 to "0" in Host to PCI Bridge Configuration Register.
B22	AH22	TURBO	Set Register 93 bit 2 to "0" in Host to PCI Bridge Configuration Register
		EXTSMI#	Set Register 93 bit 2 to "1" in Host to PCI Bridge Configuration Register.
N5	U5	IIRQA	If PCI IDE channel 0 operates in Native mode.
		IRQ14	If PCI IDE channel 0 operates in compatibility mode.
V5	M5	IIRQB	If PCI IDE channel 1 operates in Native mode.
		IRQ15	If PCI IDE channel 1 operates in compatibility mode.
D20	AF20	GPCS1	Set register 6D bit 6 to "0" in PCI to ISA Bridge Configuration Register.
		SIRQ	Set register 6D bit 6 to "1" in PCI to ISA Bridge Configuration Register.

 

4. Ball Connectivity Testing

SiS Chip will provide a NAND chain Test Mode. In order to ensure the connections of balls to tracks of mainboard, SiS Chip provides a simple way to do connective measurements. Basically, an additional 2-input-NAND gate is added into the I/O buffer cells. And, one of inputs of NAND gate is connected to input pin of I/O buffer as test input port in test mode. To monitor the test result at test output port, the output of the NAND gate is connected to the other input of the next NAND gate. Such that, the test result could be propagated and it forms a NAND tree, as depicted in Figure 3-35 on page *. To adapt to the scheme, all output buffers of SiS Chip are changed to bidirection buffers to accept test signals.

1. Test Scheme

There are six NAND tree chains are provided by SiS Chip. Each NAND tree chain has several test-input pins and one output pin.

The following description is an example on 4-test-input pins to explain a NAND tree chain test scheme.

First of all, logic LOW is driven into TESTIN1 pin from track on mainboard. If logic HIGH could be observed at TESTOUT pin, it means that the connection of TESTIN1 pin to track is good, as shown in Figure 3-36 on page *. To test TESTIN2 pin, TESTIN2 pin should be driven LOW also. And, TESTIN1 pin should be kept at logic HIGH, such that the test result could be passed to TESTOUT pin and so on. Although SiS Chip operates at 3.3V, all input buffers of SiS Chip are 5V-input tolerance. Hence, all test signal could go up to 5V.

2. Measurements